References: <3DDED492.2B9873B0@webaccess.net> <3DDFD4C6.4E2AD8F2@webaccess.net>
Subject: Re: Phase locked loops and confusion.
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Date: Sat, 23 Nov 2002 19:36:07 GMT
NNTP-Posting-Date: Sat, 23 Nov 2002 14:36:07 EST
Organization: Cox Communications
"Chuck Simmons" wrote in message
> Mike wrote:
> > "Chuck Simmons" wrote in message
> > news:3DDED492.2B9873B0@webaccess.net...
> > > PLLs are fairly common and seem fairly simple but I found over the
> > > week that confusion abounds and since I have seen this confusion
> > > I wonder if it is common.
> > Yes, it's common, and not just among digital engineers, although since
> > digital engineering doesn't require a knowledge of control systems, it's
> > probably more common, in general, for digital engineers not to
> > PLLs.
> > On the other hand, digital control systems engineers regularly take
> > into account in their control systems, since it's a natural part of the
> > z-transform. Analog designers rarely include delay, and tend to make the
> > system bandwidth low enough that the delay won't significantly affect
> > stability or the response. If performance is critical, the low-bandwidth
> > approach is less than optimal; a z-transform model is often a better
> > approximation.
> System modeling is vaguely the issue here however the modeling method
> whether Laplace transformation, z-transform, state space or what have
> you is not the issue. In control theory terms, it is really a case of
> plant identification.
I understand. Since I normally think of the phase detector as a simple Kp, I
had to reread your description a couple times before I realized what they
were doing. My comment about the digital engineers was aimed more at some of
the other posts, which seem to suggest that the problem is inherent in
-- Mike --