From: Chuck Simmons
Organization: You jest.
X-Mailer: Mozilla 4.61 [en] (X11; U; Linux 2.0.33 i586)
Subject: Re: Phase locked loops and confusion.
Date: Sat, 23 Nov 2002 19:51:51 GMT
NNTP-Posting-Date: Sat, 23 Nov 2002 11:51:51 PST
Jim Thompson wrote:
> On Sat, 23 Nov 2002 01:06:45 GMT,
> Chuck Simmons ,
> In Newsgroup: sci.electronics.design,
> Article: <3DDED492.2B9873B0@webaccess.net>,
> Entitled: "Phase locked loops and confusion.",
> Wrote the following:
> |PLLs are fairly common and seem fairly simple but I found over the past
> |week that confusion abounds and since I have seen this confusion before,
> |I wonder if it is common.
> For a good phase detector see...
> Newsgroups: alt.binaries.schematics.electronic
> Subject: Phase/Frequency Detector - DualD-PFD.pdf
> Message-ID: <firstname.lastname@example.org>
I consider the phase detector a given in that the actual detailed design
of it is not interesting given I am assured that the output of the phase
detector is an integer proportional to phase error.
> Phase detectors don't have integrators, but VCO's are represented by
This was the problem in that the designers, cribbing from working analog
circuits produced a more or less exact digital equivalent. The circuits
they cribbed from collapsed an integrator into the phase detector.
> Thus, if you add any filter at all, it *must* be lead-lag, or it's
Not true. A single integrator loop is stable and doesn't need a
stabilizing filter. Two integrators require at least a 1st order
> Why don't you post the complete PLL system requirements, type of input
> signal, type of output signal, frequencies; is it 1:1, or is there a
> divider in the loop?
It's a clock recovery system. There are two PLLs actually involved. One
has inputs of 44kHz to a couple of megaHertz using various divide ratios
and has requirements on bandwidth that depend on the data modulation
method which may be FM or phase. The output frequency may be a bit over
200MHz. The other is harmonically locking on an RLL code to recover the
read clock and design goals require at least 200MHz output and more than
double that in a year (assuming a process change). Phase accuracy is
pretty important because it contributes to bit error rate which probably
needs to be better than 1 error in 10^5 bits read. One wants an end user
error rate of maybe 1 error in 10^14 bits although two orders of
magnitude lower is acceptable. All of this is industry standards we have
to follow as we do not make an end user product at all (we would need
our heads examined if we tried something that stupid).
> Then we can see who, in this group, really knows PLL's ;-)
There seem to be several. Kevin has a strong grip on both the analog
side and how it might apply in clock recovery which is a well worn
problem. It does crawl out of the woodwork sometimes in odd places,
... The times have been,
That, when the brains were out,
the man would die. ... Macbeth
Chuck Simmons email@example.com