From: John Larkin
Subject: Re: Phase locked loops and confusion.
Date: Sat, 23 Nov 2002 11:55:45 -0800
Organization: Posted via Supernews, http://www.supernews.com
X-Newsreader: Forte Agent 1.91/32.564
On Sat, 23 Nov 2002 19:23:57 GMT, "Mike" wrote:
>"Kevin Aylward" wrote in message
>> John Larkin wrote:
>> > My favorite phase detector is a d-type flipflop operating in bang-bang
>> > mode: input signal on clock, reference osc on D. This is really
>> > interesting to analyze and to design a filter for. Gain is infinite,
>> > sort of.
>> But if you require low jitter, a bang bang is not very effective.
>I think you'll find that John's jitter is enviously low - we talked about
>his PLL in a thread (about calculus, I think) a couple months back.
>The difficult thing about the bang-bang phase detector is that the gain is
>effectively infinite when there's no noise in the system; as the noise
>increases, the gain decreases. This characteristic makes it rather difficult
>to do traditional loop analysis, but if you analyze a noise free system with
>an ideal bang-bang phase detector, it will exhibit a limit cycle whose
>amplitude is a function of the other loop parameters.
>The nice thing about the bang-bang phase detector in a digital system is
>that the phase detector can be clocked by the same clock used to clock the
>rest of the system. That means it can be synthesized (as in digital
>synthesis tools) - a huge advantage in many digital systems.
>-- Mike --
the other nice thing is that the phase error can be kept very small.
If, say, you want to run a system at a 155 MHz clock rate (ie, lock to
OC3 data) and keep the time drift below 1 ps, the phase detector has
to be stable to 1 part in 6000, which is tough to do with any linear
electronics, much less fast stuff. A bangbang phase detector using a
differential EclipsLite flipflop can hold 1 ps easily.
I did a thing like this for the NIF laser, and the PLL contribution to
jitter and wander is just about 1 ps RMS; the whole system comes in
around 3 ps. Of course, we used a very good VCXO and had a fairly
narrow lock range requirement; bangbang is pretty obviously a nasty
approach for wideband loops.
I've always wanted to try a loop using a sampling phase detector; that
should be interesting. It's also fun to use an ADC as the phase
detector; then you can do cool PID-type loops in an FPGA or whatever.