From: Chuck Simmons
Organization: You jest.
X-Mailer: Mozilla 4.61 [en] (X11; U; Linux 2.0.33 i586)
Subject: Re: Phase locked loops and confusion.
References: <3DDED492.2B9873B0@webaccess.net> <3DDFDC40.DBB1240D@webaccess.net>
Date: Sat, 23 Nov 2002 21:48:20 GMT
NNTP-Posting-Date: Sat, 23 Nov 2002 13:48:20 PST
Jim Thompson wrote:
> On Sat, 23 Nov 2002 19:51:51 GMT,
> Chuck Simmons ,
> In Newsgroup: sci.electronics.design,
> Article: <3DDFDC40.DBB1240D@webaccess.net>,
> Entitled: "Re: Phase locked loops and confusion.",
> Wrote the following:
> |Jim Thompson wrote:
> |> On Sat, 23 Nov 2002 01:06:45 GMT,
> |> Chuck Simmons ,
> |> In Newsgroup: sci.electronics.design,
> |> Article: <3DDED492.2B9873B0@webaccess.net>,
> |> Entitled: "Phase locked loops and confusion.",
> |> Wrote the following:
> |> Phase detectors don't have integrators, but VCO's are represented by
> |> Kv/s.
> |This was the problem in that the designers, cribbing from working analog
> |circuits produced a more or less exact digital equivalent. The circuits
> |they cribbed from collapsed an integrator into the phase detector.
> |> Thus, if you add any filter at all, it *must* be lead-lag, or it's
> |> unstable.
> |Not true. A single integrator loop is stable and doesn't need a
> |stabilizing filter. Two integrators require at least a 1st order
> |stabilizing filter.
> You still misunderstand. A VCO *is* an integrator all by itself. Add
> a filter and you've added another pole... you need a zero in there
That was my point. I didn't add the second integrator. It was added by
someone else years ago and accurate cribbing of the circuit brought it
along. My point was ... never mind. I see exactly why the other
engineers were confused.
> |> Why don't you post the complete PLL system requirements, type of input
> |> signal, type of output signal, frequencies; is it 1:1, or is there a
> |> divider in the loop?
> |It's a clock recovery system. There are two PLLs actually involved. One
> |has inputs of 44kHz to a couple of megaHertz using various divide ratios
> |and has requirements on bandwidth that depend on the data modulation
> |method which may be FM or phase. The output frequency may be a bit over
> |200MHz. The other is harmonically locking on an RLL code to recover the
> |read clock and design goals require at least 200MHz output and more than
> |double that in a year (assuming a process change).
> You can do that all digitally.
Not entirely. To do a so called digital PLL, you have to use a base
oscillator that is very high in frequency. For low raw error rate, this
can translate to over a gigahertz for a 100MHz clock if update holes can
reach the typical length in some RLL codes. This is usually solved with
a ring oscillator designed as a VCO and an analog loop (this is
extremely common in digital chips that have a synthesizer and even more
common in clock recovery from data). In looking at current products in
our area, we don't see anybody using purely digital PLLs. We suppose
this is a cost issue. We would have to go to a nasty process to get the
really high speed for it.
... The times have been,
That, when the brains were out,
the man would die. ... Macbeth
Chuck Simmons email@example.com