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From: Jim Thompson
Subject: Re: Phase locked loops and confusion.
References: <3DDED492.2B9873B0@webaccess.net> <3DDFDC40.DBB1240D@webaccess.net> <3DDFF78D.41F636E9@webaccess.net>
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Date: Sat, 23 Nov 2002 21:51:39 GMT
NNTP-Posting-Date: Sat, 23 Nov 2002 16:51:39 EST
Organization: Cox Communications
On Sat, 23 Nov 2002 21:48:20 GMT,
Chuck Simmons ,
In Newsgroup: sci.electronics.design,
Entitled: "Re: Phase locked loops and confusion.",
Wrote the following:
|Jim Thompson wrote:
|> |It's a clock recovery system. There are two PLLs actually involved. One
|> |has inputs of 44kHz to a couple of megaHertz using various divide ratios
|> |and has requirements on bandwidth that depend on the data modulation
|> |method which may be FM or phase. The output frequency may be a bit over
|> |200MHz. The other is harmonically locking on an RLL code to recover the
|> |read clock and design goals require at least 200MHz output and more than
|> |double that in a year (assuming a process change).
|> You can do that all digitally.
|Not entirely. To do a so called digital PLL, you have to use a base
|oscillator that is very high in frequency. For low raw error rate, this
|can translate to over a gigahertz for a 100MHz clock if update holes can
|reach the typical length in some RLL codes. This is usually solved with
|a ring oscillator designed as a VCO and an analog loop (this is
|extremely common in digital chips that have a synthesizer and even more
|common in clock recovery from data). In looking at current products in
|our area, we don't see anybody using purely digital PLLs. We suppose
|this is a cost issue. We would have to go to a nasty process to get the
|really high speed for it.
Try IBM 8HP SiGe BiCMOS, Ft~210 GHz ;-)
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| Jim-T@analog_innovations.com Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
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