The Cyber-Spy.Com Usenet Archive Feeds Directly
From The Open And Publicly Available Newsgroup
This Group And Thousands Of Others Are Available
On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic,
Opinions Or Content Posted To This Or Any Other
Newsgroup. This Web Archive Of The Newsgroup And
Posts Are For Informational Purposes Only.
From: Chuck Simmons
Organization: You jest.
X-Mailer: Mozilla 4.61 [en] (X11; U; Linux 2.0.33 i586)
Subject: Re: Phase locked loops and confusion.
References: <3DDED492.2B9873B0@webaccess.net> <3DDFDC40.DBB1240D@webaccess.net> <3DDFF78D.41F636E9@webaccess.net> <email@example.com>
Date: Sat, 23 Nov 2002 22:37:48 GMT
NNTP-Posting-Date: Sat, 23 Nov 2002 14:37:48 PST
Jim Thompson wrote:
> On Sat, 23 Nov 2002 21:48:20 GMT,
> Chuck Simmons ,
> In Newsgroup: sci.electronics.design,
> Article: <3DDFF78D.41F636E9@webaccess.net>,
> Entitled: "Re: Phase locked loops and confusion.",
> Wrote the following:
> |Jim Thompson wrote:
> |> |It's a clock recovery system. There are two PLLs actually involved. One
> |> |has inputs of 44kHz to a couple of megaHertz using various divide ratios
> |> |and has requirements on bandwidth that depend on the data modulation
> |> |method which may be FM or phase. The output frequency may be a bit over
> |> |200MHz. The other is harmonically locking on an RLL code to recover the
> |> |read clock and design goals require at least 200MHz output and more than
> |> |double that in a year (assuming a process change).
> |> [snip]
> |> |Chuck
> |> You can do that all digitally.
> |Not entirely. To do a so called digital PLL, you have to use a base
> |oscillator that is very high in frequency. For low raw error rate, this
> |can translate to over a gigahertz for a 100MHz clock if update holes can
> |reach the typical length in some RLL codes. This is usually solved with
> |a ring oscillator designed as a VCO and an analog loop (this is
> |extremely common in digital chips that have a synthesizer and even more
> |common in clock recovery from data). In looking at current products in
> |our area, we don't see anybody using purely digital PLLs. We suppose
> |this is a cost issue. We would have to go to a nasty process to get the
> |really high speed for it.
> Try IBM 8HP SiGe BiCMOS, Ft~210 GHz ;-)
No way. Too expensive. Nobody else in our game is doing it so we can't.
It's that simple. You never want to be the high cost solution.
I know about what a mask set for SiGe costs. That's really ugly NRE if
there is any way at all around it. (I think I heard that SiGe runs to
something like 40 masks. That's beyond ugly.)
... The times have been,
That, when the brains were out,
the man would die. ... Macbeth
Chuck Simmons firstname.lastname@example.org
Go Back To The Cyber-Spy.Com
Usenet Web Archive Index Of
The sci.electronics.design Newsgroup