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From: Fred Bloggs
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Subject: Re: zero-power toggle circuit; was, how to master electronics
References: <email@example.com> <firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org> <email@example.com> <3DDFAF13.firstname.lastname@example.org> <3DDFF582.email@example.com> <firstname.lastname@example.org>
Date: Sun, 24 Nov 2002 02:21:28 GMT
NNTP-Posting-Date: Sat, 23 Nov 2002 18:21:28 PST
Organization: EarthLink Inc. -- http://www.EarthLink.net
Tony Williams wrote:
> In article <3DDFF582.email@example.com>,
> Fred Bloggs wrote:
>>Right- that's always a problem- even for the paralleled 4049 but maybe
>>not of this magnitude. In operation at the supply voltages you describe,
>>the left inverter output should transition between the supply rails in
>>under 50ns which means say at 15V the "shoot-through" region will be
>>traversed in 50/3=17ns. I am not so sure those slow-poke 2N440x's will
>>go from 0 to 60MPH in that time frame-as a matter of fact, the diffusion
>>capacitance alone is 21nF at 500mA. So the crowbar will more likely be
>>1/10 of your estimate.
> Hang on Fred, I've just noticed something......
> Those 5.6k's etc is a quite a neat looking trick,
> (worth remembering, especially for single ended o/p).
> But at the end of the day those output transistors
> are actually being driven as darlingtons. So the Vout
> to the big external MOSFET will always go to no better
> than a Vbe away from the rails. That circuit also has
> no zero current state... it will always draw Vbe/5.6k.
> In which case the transistors can just as well be
> used as a normal pnp/npn emitter follower pair, which
> will have the same Vout capability, but without the
> shoot-through problem.
> Add a 4k7 between bases and emitters, so that (when
> the transistors have finished their fast thrash) the
> CMOS can push Vout fully to the rails (and shut down
> both bipolar transistors).
> Note to Win (just to make your day). I think the 4007A
> *does* have the MOSFETs required to make the original
> 2-MOSFET RTL latch, plus the push-pull inverter for
> driving an external MOSFET.
This circuit requires more examination. Take the case of pulling the
output high to turn the power P-FET off. The common gate input to the
CMOS makes it to Vss so that Vgs,p=Vbe-Vdd for a conducting pmos, and
Vgs,n=-Vbe,npn. Therefore, it is not possible for the pulldown nmos to
be anywhere near conducting when the npn is conducting and Vg=Vss, and
the p-channel and PNP supply pure leakage current. So the circuit does
make it to zero current quiescent, and the outputs do make it
negligibly close to the rails.
I ran the circuit at Vdd=15V and Vss=0V. There is absolutely no
shoot-through between the external transistors at switch-over. I even
hung a 10pF at the output of the left inverter to slow the rise time to
50ns. The CMOS shoot-through rises to 7.5mA and the off-transistor
emitter currents are under 100uA going either way. There is a minor
surprise. For example with the output making the H->L transition, the
output across 10nF load decays to zero in 400ns. The npn pull-down
current peaks at 500mA at the 220ns mark, the pnp current starts to
cut-in at 150ns (when Vout=11V), reaching a peak of 30mA at 370ns (when
Vout~0), and then decaying to zero by 520ns-about the same time as the
npn current has decayed to zero- going through a definite slope increase
non-linearity at the 375ns point. So this is definitely a delayed
shoot-through of 30mA scale-and this occurs well after the CMOS has
reached solid cut-in and cut-off levels. It appears that the output
voltage negative slew is coupling through Cgd to turn the pmos on ever
so slightly- and this effect is amplified by the pnp current gain- as
Win suspected- but in an entirely unexpected manner. And AH!!- cutting
the gain by reducing the source resistors to 2.7K reduces the effect to
3mA with no real change in output fall time. Removing the 10p at the
output inverter gate for safety measure doesn't alter that picture either.
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