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From: Chuck Simmons
Organization: You jest.
X-Mailer: Mozilla 4.61 [en] (X11; U; Linux 2.0.33 i586)
Subject: Re: Phase locked loops and confusion.
References: <3DDED492.2B9873B0@webaccess.net> <3DDFDC40.DBB1240D@webaccess.net> <3DE00932.E1A4D1CB@ieee.org>
Date: Sun, 24 Nov 2002 02:45:35 GMT
NNTP-Posting-Date: Sat, 23 Nov 2002 18:45:35 PST
> Chuck Simmons, Jim Thompson wrote:
> >> Why don't you post the complete PLL system requirements, type of
> >> input signal, type of output signal, frequencies; is it 1:1, or is
> >> there a divider in the loop?
> > It's a clock recovery system. There are two PLLs actually involved.
> > One has inputs of 44kHz to a couple of megaHertz using various divide
> > ratios and has requirements on bandwidth that depend on the data
> > modulation method which may be FM or phase. The output frequency may
> > be a bit over 200MHz.
> What application requires this? Are you designing a controller for
> a drive that handles both audio and video? Is this part of an over-
> sampling scheme where you end up converting parallel data to a serial
> stream to simplify the analog recovery filters? What are the bandwidth
> and modulation requirements of the VCO?
OK, CD and DVD. Writable and rewitable devices.
> > The other is harmonically locking on an RLL code to recover the read
> > clock and design goals require at least 200MHz output and more than
> > double that in a year (assuming a process change).
> So you are part of a team designing a drive controller for reading (and
> writing?) RLL encoded data from/to a CD or DVD. As an analog guy I am
> a little hazy on how this is done these days. What RLL encoding schemes
> do you need to support, 2/7, 4/7, or something newer?
This is a moving target. There are about 6 or 7 standards right now and
the goal is to support all that look like they have a future. The
controller is done and has been for about a year (except for tweaks).
The read channel is much more interesting (read horrifying) because
sensors, media and standards change with every slight breeze. Another
new standard popular in China came along a few weeks ago. A moving
> > Phase accuracy is pretty important because it contributes to bit error
> > rate which probably needs to be better than 1 error in 10^5 bits read.
> So how much trouble is it to quickly synchronize the PLL after a drive
> head seek occurs? Does that make the subsequent job of holding phase
> steady more difficult? In that regard would it help your designs to
> low pass filter the signal to the VCO, or is that too simplistic an
> approach because of other troubles it would cause?
No problem because we can do zero phase restart in a couple of different
ways. That's been a no brainer for years. Some things came up in this
group that make me think a little differently. I have a new strategy for
both the phase detector and the filter. I'll see Monday if the designers
buy it. A little sleep on it and they may have already seen what they
> > One wants an end user error rate of maybe 1 error in 10^14 bits
> > although two orders of magnitude lower is acceptable. All of this
> > is industry standards we have to follow as we do not make an end
> > user product at all (we would need our heads examined if we tried
> > something that stupid).
> The way the system error budget works isn't it true that the tighter
> the controller holds the timing window the "mushier" (read cheaper)
> the drive hardware can be?
You mean read channel. The controller is a whole 'nother animal. A big
honking chip really. I don't see what you are saying. Getting mushy is
getting bad. What we know is that we have to be able to read illegal
disks. That's a major stretch.
> I have some experience with phaselock loops for motor control where
> the motor/digital tach signal (the VCO) is fed into one input of an 8
> bit up/down counter and the reference frequency is fed into the other.
> Its 8 bits then feed a DAC ladder network to generate an integrated
> frequency error signal. I was intrigued to see if I could draw any
> useful analogies to your system, but I still really only have a vague
> idea what all you are up to.
Simple clock recovery. Spin was interesting, however. Doing CLV was
challenging for me since in hard drives, I had always done head
positioning (20 years of that). Variable sample rate took a bit of
BTW, I don't control the design. They tell me they have what looks like
an analog problem. I say what I think might help. I'm not the only one.
I have a sore ear from talking to the other guy on the phone. He's
pissed at me because I fell asleep during a presentation he gave. I
think two people stayed awake somehow. I learned 40 years ago that
presentations are soporific - I consider 5 slides max for a
presentation. Three slides if it is right after lunch.
... The times have been,
That, when the brains were out,
the man would die. ... Macbeth
Chuck Simmons email@example.com
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