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From: Tony Williams
Subject: Re: zero-power toggle circuit; was, how to master electronics
Date: Mon, 25 Nov 2002 07:07:24 +0000 (GMT)
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NNTP-Posting-Date: Mon, 25 Nov 2002 07:49:53 +0000 (UTC)
User-Agent: Pluto/1.14i (RISC-OS/3.60)
In article <3DE14490.email@example.com>,
Fred Bloggs wrote:
> Tony Williams wrote:
> > Might be interesting to see what happens if that
> > bottom-left N-Fet is disconnected and replaced
> > with a 10k pulldown.
> ............... If you want the circuit to power up OFF then
> disconnecting the bottom left N-fet does not help, if I understand you
> correctly. But adding a 10K pull-down to the inverter output makes the
> turn-on state OFF under any circumstances.
I had this crafty plan..... show that putting a
10k in instead of one of the transistors would get
a reliable power-up state. Then put the transistor
back in across the R and show that it was still
But you jumped to the final answer in one swipe.
> I ran the circuit through its paces with the IRF9513, Cgs=2.3nf,
> and went so far as adding an external 10nf G-D, with power supply
> applied monotonically in the range 10u-> 1s rise times. The circuit
> goes into OFF every time. I also ran the DC transfer on the two
> inverters in cascade with 10k pulldown, and this explains everything.
> The 10k divides the first inverter gain by 20-50% and this disparity
> is amplified by the second feedback inverter to force the combination
> dead off at Vdd>=1.9V. I think this is enough margin to go with despite
> not being able to tolerance and simulate two separate inverters which
> are cut from the die cloth anyway.
I was coming at it from a more simplistic direction.
At low Vcc the gate's ON resistance is so poor that
(with a pullup/pulldown R) the gate is RTL, and the
10k guides the gate into the required power-up state.
There could be no need for a big sideways RC to kick a
2-gate bistable into the required power-up state.
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