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From: "petrus bitbyter"
Subject: Re: HDD address decoding
X-Newsreader: Microsoft Outlook Express 5.50.4807.1700
Date: Mon, 25 Nov 2002 20:29:46 GMT
NNTP-Posting-Date: Mon, 25 Nov 2002 21:29:46 MET
Organization: chello broadband
"Paul Taylor" schreef in bericht
> I am designing an embedded board that takes an ISA bus and provides a box
> header to take a standard PC IDE hard drive. As far as I can see, I can
> connect up most of the IDE signals to the ISA bus. I need to generate
> the two IDE chip selects, CS0 and CS1. What addresses do these need to
> decode to?
You CS0 and CS1 are often called -CS1FX and -CS3FX and connected to pin 37
an 38 of the IDE-connector respectively. Both signals are active low and
they should not be active at the same time.
When -CS1FX is active the addresses are mapped at 01 1111 0xxx b.
So 1F0-1F7, the x's are determined by the DA0-DA2 lines.
When -CS3FX is active the addresses are mapped at 11 1111 0xxx so 3F0-3F7.
> I have got a PC memory map which says:
> 1F0-1F8 Fixed disk controller 1
> 170-177 Fixed disk controller 2
The second disk controller uses 170-177 and 370-377.
> Only one disk will ever be plugged into my system. Is CS0 for fixed disk
> 1 and CS1 for fixed disk 2?
> Is there a reason why fixed disk 1 reserves 9 addresses when there is
> only 3 address lines (and therefore can only address 8 locations) going
> to the IDE connector?
In the days of the first PC's they often used more addresses then required
to make addressdecoding easier (=cheaper). They thought to have addresses
enough to justify this spill. (They also thought 640kByte of memory was all
a PC would ever need.)
> Paul Taylor
For (much) more info Google for ATA interface.
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