From: "John Jardine"
Subject: Re: circuit wanted-SQUARE PULSE GENERATOR
Date: Tue, 26 Nov 2002 14:41:35 -0000
References: <1038144646.265208@athprx02> <email@example.com> <firstname.lastname@example.org>
NNTP-Posting-Date: 26 Nov 2002 14:29:48 GMT
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Winfield Hill wrote in message
> Tony Williams wrote...
> > Winfield Hill email@example.com wrote:
> >> ... internal resistance below 1V, so R4 and C2 provide a
> >> fixed 25us time for thoroughly discharging C each cycle.
> > I'm still trying to see why that 25uS discharge time
> > doesn't result in a 2.5% non-linearity in the control.
> > Knowing you, you have it covered somewhere, but I just
> > can't see where. Must be going thick...........
> No, Tony, you have found me out! It's unavoidably there, a
> [1/(1 + 2.5% Vin/Vmax)] term in the frequency formula. :>)
> The discharge could be shortened to 5 or 10us, but it'd still
> be there. Fixing the issue would require a switched negative
> tracking current sink. And the added complexity (two opamp-
> controlled current sources, two steering diodes) would likely
> force one to abandon the cmos 555 approach entirely, choosing
> instead a opamp triangle integrator / comparator scheme, etc.
> There's another fault to my circuit. The O.P. specified a
> "square wave." If we assume he meant 50% duty cycle, rather
> than simply rectangular logic pulses, the 25us negative-going
> pulses my circuit puts out are not acceptable. On the other
> hand, modifying the circuit with the above-mentioned tracking
> current sink would also solve this issue.
> - Win
Or just use a charge balancing V/F setup, eg, if in I.C. form, the
exceedingly good, Telcom TC9400.
(10T pots c/w counters can of course be replaced by decade/bcd
switches/thumbwheels using fixed resistors).