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From: Fred Bloggs
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Subject: Re: ? Binary to BCD conversion chip ?
References: <firstname.lastname@example.org> <3DE5D8B5.EF8930F3@scazon.com> <email@example.com>
Date: Thu, 28 Nov 2002 17:06:07 GMT
NNTP-Posting-Date: Thu, 28 Nov 2002 09:06:07 PST
Organization: EarthLink Inc. -- http://www.EarthLink.net
Tony Williams wrote:
> In article <3DE5D8B5.EF8930F3@scazon.com>,
> Paul Burke wrote:
>>There is an algorithmic way to do the conversion on an incoming stream
>>of data. All I can remember about it was that it was in an old
>>programmable logic applications book (over 15 years ago)- perhaps MMI? A
>>colleague implemented it in software on a 6809 and all I can say is it
>>worked, and saved a few vital bytes compared with divides or repeated
>>subtraction. Took an age though.
> I think there's an example in a PIC app note.
It's a bit-instruction intensive add-3 algorithm that requires shifting
of the BCD result nibbles. It iteratively multiplies the BCD nibbles by
shift lefts but before this is done each nibble must have 3 added to it
if >5- a simple variant of the add-6 decimal adjust.
There was a 74XXX MSI that performed the conversion nibble-wise
combinatorially- but the number of chips required grew as some
ridiculous thing like 10^(nibbles) or something unusable like that.
If the number of digits is large then the answer is a uproc. If it's
small like 2-4 digits then a CPLD using a simple counter algorithm is
far more useful than EPROM. For an 8-bit binary to 12-bit BCD, this is
only 20 bits, and say 7 bits for a BCD-7-segment encoder for subtotal 27
bits, leaves 9 macrocells open for display mux'ing, input latching, and
other tasks in the low-end Xilinx XC9536-15PC44C from Xilinx at $3.30
unit quantity available from their website or DigiKey. The fitting and
design software is free- handles nearly any reasonable design entry
method, but the parallel port programming cable is a bit pricey at $95.
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