From: Chris Carlen
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Subject: Re: PLL phase detector in CPLD
Date: Mon, 09 Dec 2002 00:49:45 GMT
NNTP-Posting-Date: Sun, 08 Dec 2002 16:49:45 PST
Ken Smith wrote:
>>else in the parts, which helps too. It seems to me that if you use a
>>charge-pump type of output, or if you maintain a reference based on
>>some tied-high and tied-low CPLD outputs, you can get quite good power
> If by this you mean what I call a tri-state phase detector, there can be
> Many CPLDs have "bus-keeper" circuits. Dont forget to turn them off in
> your design.
> Some CPLDs have much higher Icc values if the pins are at middle levels.
Are you thinking of a "Z-state" detector, aka., 4046 (the other
detector, not the XOR gate) in which the output actually goes high-Z?
The 3-state detector I'm thinking of has no high-Z output condition. It
is a 3-state PD, that's all. Hmm, I don't have my PLL text here to
state the title.
> I'd also like to add the suggestion that an analog switch be used as the
> buffer. This means that only the actual signal has to be at an exact
> voltage and not the power supply. It also allows much easier tri-state
> filter designs. If you are doing a tri-state design beware of the CD405X
> series of analog switches. If you change the select lines on these
> without disabling them during the change, you can get a huge charge
> injection. This tends to push the phase to a slight offset when the loop
Hmm, an analog switch is a neat idea. Thanks.
Christopher R. Carlen
Suse 8.1 Linux 2.4.19