From: "Christopher R. Carlen"
Subject: How to increase PLL order?
Date: Mon, 09 Dec 2002 12:39:50 -0800
Organization: Sandia National Laboratories, Albuquerque, NM USA
NNTP-Posting-Date: Mon, 9 Dec 2002 19:38:01 +0000 (UTC)
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I am working with PLLs containing motors. I have been using a
"zero-pole" loop filter with my motor/VCO, so that I have transfer
functions of the elements of the loop which look something like this:
Hmotor(s)=(1/(LC))/(s^2+(R/L)s+1/(LC)s)*N/Kv in (rad/V)
where R and L are those ot the motor windings, and C is an equivalent
capacitance to the total moment of inertia of the motor, N is the number
of rotation detector pulses per rev., and Kv is the motor voltage
constant in V/(rad/s). These parameters are empirically measured, and
have typical values of R=2.6ohm, L=0.6mH, C=0.16F, and Kv=0.013V/(rad/s)
for the motor I'm using.
Notice the extra s in the denominator, corresponding to the integration
of the VCO (converting frequency to phase). Thus, I use a phase
detector transfer function of simply a constant Kp in (V/rad).
My loop filter transfer function looks like:
where Kf is the DC gain, and wz and wp are the zero and pole
frequencies, respectively. By placing the zero and pole around the
frequency where I want the open loop gain to be 1, I can reduce the
slope of the open loop gain through the unity gain frequency, so that
the loop is stable. At least that's what AoE says to do, and it is
consistent with the procedures described in the Unitrode U113 app. note
on motor control with PLL.
It seems to work very well, where I can empirically select a unity gain
frequency, calculate the filter components to center the pole and zero
(logarithmically) around it, plot lots of neat graphs, then turn on the
real hardware. I get a good step response to input frequency changes,
with minimal or considerable overshoot, depending where I place the
unity gain f.
The problem is that this loop doesn't integrate the phase error to zero,
which has not been a problem for the application that I have been
designing so far, but will be a problem in a future application where I
will need to control the absolute phase difference between two different
motors, and so each PLL will need to run with (very close to) zero phase
error relative to the input frequency references.
The question is then how to change my filter so as to add integration,
but also to satisfy the criteria for loop stability?
I haven't yet tried plotting open loop gain graphs with the added order
of loop transfer function, because I am puzzled as to how to add the
It seems I could put the integrator in series with the existing loop
filter, in which case I'd change the total filter transfer function to
Hf(s)=Kf*(1+s/wz)/(1+s/wp) * Ki/s
Or I could split the phase detector signal, and sent it to both the
existing loop filter, and an integrator, then sum the result, yielding a
PI controller within the PLL:
Hf(s)=Kf*(1+s/wz)/(1+s/wp) + Ki/s
Which one of these methods is the right one, or am I heading out to left
field here, and to increase the order of the loop I must do something
substantially different than what I'm thinking?
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA