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From: email@example.com (Bill Sloman)
Subject: Re: How to increase PLL order?
Date: 10 Dec 2002 14:40:50 -0800
NNTP-Posting-Date: 10 Dec 2002 22:40:50 GMT
"Kevin Aylward" wrote in message news:...
> Christopher R. Carlen wrote:
> > Hi:
> > The problem is that this loop doesn't integrate the phase error to
> > zero, which has not been a problem for the application that I have
> > been designing so far, but will be a problem in a future application
> > where I will need to control the absolute phase difference between
> > two different motors, and so each PLL will need to run with (very
> > close to) zero phase error relative to the input frequency references.
> If you want the steady state phase between the inputs to be zero you
> need to use a different type of phase detector. A standard digital
> frequency phase detector is probably what your after.
According to chapter 2 of Floyd M. Gardner's "Phaselock Techniques"
(ISBN 0-471-04294-3) you need a second order control loop, which is to
say an integrator in the feed-back path (in addition to the integrator
formed by the voltage-controlled oscillator) to get a zero phase error
at an arbitrary (but stable) frequency.
The nature of the phase detector has nothing to do with Christopher
Carlen's problem. A digital phase-frequency detector comes into lock
much more nicely and quite a lot faster than a simple
multiplying/exclusive-OR phase detector, but once the loop is locked
both forms of phase detector give an error signal directly
proportional to phase error, and you have to feed this into an
integrator this if you want an arbitrary voltage output (and
frequency) at zero phase error.
To get a zero phase error when tracking a linearly varying frequency
you have to go to a third order loop (with two integrators in the
feed-back path) and to get zero phase error when tracking a frequency
which is increaising or decreasing at a constantly
accelerating/decelerating rate you need a fourth order loop, and so
Bill Sloman, Nijmegen
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