From: "Christopher R. Carlen"
Subject: Re: How to increase PLL order?
Date: Tue, 10 Dec 2002 18:06:37 -0800
Organization: Sandia National Laboratories, Albuquerque, NM USA
NNTP-Posting-Date: Wed, 11 Dec 2002 01:04:51 +0000 (UTC)
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Kevin Aylward wrote:
>>I think that depends on what the transfer function of the VCO is.
> No it does not.
>>course, we are used to Kvco/s, but for motors things go haywire.
>>I am using the Z-state detector from a 4046, and it doesn't produce
>>zero phase error with a motor, though it most certainly does with a
> Then something is amiss, however, what do you mean by the Z detector?
The Z-state detector is what Dan Wolaver calls the phase comparator II
in the 4046, or other implementations.
>>The reasons are in the control theory, at which I am not yet good
>>enough to explain why this happens. But I have observed it
>>nonetheless. A crude attempt at my explaining it would go something
>>The motor/VCO transfer function is wierd, so that the loop filter
>>transfer function is not that of a simple low pass filter with a
>>finite high frequency gain. Instead it is a "zero-pole" as I have
>>OPed. This filter doesn't integrate. Phase error is thus some
> Have you actually read the data sheet?
No, I just plugged in the chip and hooked up signals randomly. :-D
Seriously, the phase detector II in the 4046 forces one to drive a
passive filter, or I suppose an OP-amp integrator would work as well.
According to Dan Wolaver, "Phase Locked Loop Circuit Design," regarding
the 4046 type II detector, "This circuit is intended to be used with a
Now the reason is the high impedance state, which has to be averaged or
low-passed before doing much of anything with it. Otherwise, you'd be
PWMing the VCO at the phase detector output frequency.
With a motor as a VCO however, the VCO transfer function forces a
radically different loop filter design, in order to stabilize the loop.
This filter response is *high-pass*. You cannot feed a 4046 phase
detector II (z-state PD) into such a loop filter, or you would end up
PWMing the motor as I said. In fact, that isn't even what happens with
the z-state PD if you feed it straight into a high pass (or actually the
zero-pole filter, as I have shown in the OP). It just doesn't work at
all because the high impedance states demand a charge storage capacitor
at the output of the PD. Hence, the statement that the detector is
designed to be used with a passive filter.
What I have actually done to make the 4046 phase det. II work with my
high-pass zero-pole loop filter, is to pull up the output of the
detector. This converts the detector into something quite different. I
feed that into a low-pass filter to smooth the pulses into something
reasonably averaged, with the pole of that filter far enough above the
loop unity gain frequency so as not to disturb the effort of the loop
filter in stabilizing the loop.
This works, but does not by any means produce zero phase error, and
again, the reason is in the control theory, not the phase detector.
The problem is that the phase detector cannot work as advertized in a
motor PLL, for reasons having to do with the control theory, which force
a particular design of loop filter, which force a different use of the
4046 PD II than what the datasheet says it should do.
The problem with using the 4046 in this manner, is that the detector
can't reset in both directions, when using the pullup. Thus, the right
thing to do is to move to a 3-state detector.
Now it is possible I suppose to incorporate the integration of the 4046
PD II into my system, ie., let it drive a passive integrator as it is
intended, then factor that 1/s into my loop stability calculations, and
see what that requires from the main active loop filter in order to get
it to work. But it cannot work with a motor, as the datasheet intends
for one to use it, because that assumes a Kvco/s VCO, which is not what
> Phase comparator I, an exclusive OR gate, provides a digital error
> signal (phase comp. I Out) and maintains 90° phase shifts at the VCO
> center frequency. Between signal input and comparator input (both at 50%
> duty cycle), it may lock onto the signal input frequencies that are
> close to harmonics of the VCO center frequency.
> Phase comparator II is an edge-controlled digital memory network. It
> provides a digital error signal (phase comp. II Out) and lock-in signal
> (phase pulses) to indicate a locked condition and maintains a 0° phase
> shift between signal input and comparator input.
> If you use Phase comparator II the loop gain will force the inputs to
> have zero phase shift, whatever the frequency.
> Kevin Aylward
> SuperSpice, a very affordable Mixed-Mode
> Windows Simulator with Schematic Capture,
> Waveform Display, FFT's and Filter Design.
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA