From: "Boris Nogoodnik"
Subject: Re: SiGe BiCMOS Analog Circuit Design Engineer
Organization: KGB, Ltd.
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Date: Wed, 11 Dec 2002 01:37:52 GMT
NNTP-Posting-Date: Tue, 10 Dec 2002 20:37:52 EST
It's just a headhunter fishing around. :)
"Jim Thompson" wrote in message
> Jeanne, Your client company is apparently clueless about
> designers. Good analog designers *rarely* do layout as well
> design. Layout is an entirely different skill.
> If your client company would consider a off-site contract
> give me a call.
> On 10 Dec 2002 13:22:37 -0800,
> firstname.lastname@example.org (Jeanne Frese),
> In Newsgroup: sci.electronics.design,
> Article: <email@example.com>,
> Entitled: "SiGe BiCMOS Analog Circuit Design Engineer",
> Wrote the following:
> |I am currently looking for an outstanding SiGe BiCMOS Analog
> |Design Engineer for the design of RF, analog and mixed-signal
> |integrated circuits in SiGe BiCMOS. This is an exciting
> |with a worldwide leader in the development of Ultra Wideband
> |chipsets and related silicon-based products at their brand
> |Design Center in the U.S. Excellent benefits, including VISA
> |sponsorship and international relocation.
> |If you would like to learn more about this position or if you
> |anyone in the industry who might be interested and qualified,
> |appreciate if you could forward this information to them
> |description at the end of this email) or have them contact me
> |Thanks in advance for your cooperation.
> |Jeanne Frese – President
> |Recruiting Services International, Inc.
> |Phone: 949-363-8149
> |Fax: 949-363-8394
> |Email: firstname.lastname@example.org
> |Web: www.recruitingservicesintl.com
> |Job Responsibilities:
> |Responsible for full-custom physical design from schematics,
> |optimization for performance/area, LVS, DRC, tape-outs and
> |documentation. He/she will be responsible for the circuit
> |performance, verification and organization of all physical
> |activity. Must have good knowledge of IC layout techniques.
> |should be familiar with appropriate Cadence CAD tools. Good
> |understanding of different layers and also some understanding
> |electrical nature. Should be familiar with design rule
> |parasitic extraction, noise and crosstalk issues, power
> |techniques, yield improvement and manufacturability issues,
> |for test techniques.
> |• Minimum of 3 years of applicable experience; 6-10 years
> |• SiGe high performance circuit design experience
> |• Knowledge of submicron design issues
> |• Physical layout design experience
> |• Solid understanding of device physics
> |• Exposure to many different circuit techniques
> |• DRC, LVS, extraction experience
> |• Knowledge of Place and Route methodologies
> |• Knowledge of static timing model formats
> |• Experience in transistor level circuits
> |• Good interpersonal skills, detail oriented, independent,
and able to
> |make good decisions
> |• MSEE or higher
> ...Jim Thompson
> | James E.Thompson, P.E. | mens
> | Analog Innovations, Inc. | et
> | Analog/Mixed-Signal ASIC's and Discrete Systems | manus
> | Phoenix, Arizona Voice:(480)460-2350 |
> | Jim-T@analog_innovations.com Fax:(480)460-2142 | Brass
> | http://www.analog-innovations.com | 1962
> For proper E-mail replies SWAP "-" and "_"
> I love to cook with wine. Sometimes I even put it in the