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From: Chris Carlen
User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.1) Gecko/20020826
X-Accept-Language: en-us, en
Subject: Re: How to increase PLL order?
Date: Wed, 11 Dec 2002 04:39:05 GMT
NNTP-Posting-Date: Tue, 10 Dec 2002 20:39:05 PST
Jim Thompson wrote:
> |A 4046 type II (digital/charge pump) detector driving an R-C or R-C//C
> |filter does give a type 2 closed loop: zero steady-state phase error.
> Absolutely! Methinks Chris has some cockpit errors in his
> experimental setup.
> ...Jim Thompson
I never said I was driving an RC filter! Of course it will produce zero
phase error with a RC filter, which integrates. But I am not driving an
RC filter with it, but rather converting it into a strange sort of phase
detector which produces a voltage proportional to the phase difference
*without* integrating by pulling up on the z-state's output, then
feeding to an RC with a pole at quite a high frequency, relative to the
loop's unity gain frequency.
Thus, my phase detector is effectively not a charge pump anymore,
because of the pullup resistor. It is little different from a 2-state
detector, I think. I have to look at the book tomorrow, I think I get 0
to VCC vs. 0 to 2 pi phase difference.
Think about what happens when you put a pullup resistor on the output of
a 4046 phase detector #2 folks! That changes everything.
Why would I do such a crazy thing? Read U113. Then think about what
would happen if you fed a 4046 phase det. #2 output into the loop filter
that works with a motor PLL.
It doesn't work, because there's no integrator, which is required to use
the #2, unless you do something off the wall like I did to convert into
something *other* than a charge pump digital memory z-state 4046 #2
And that is the point of my question which is: since the motor PLL is
very different from a Kvco/s type of PLL, the loop filter is very
different as a result. The filter is not compatible with a 4046 #2 PD.
The PLL design indicated in U113 doesn't integrate phase error to zero
because it doesn't have to. I wish to extend it's capabilities to
having zero phase error. That requires sticking in an integrator. But
doesn't that raise questions about loop stability? Yes--you can't just
go sticking in another pole without changing the slope of the open loop
gain through the unity gain frequency and/or changing the phase margin.
Hence the subject "how to increase PLL order?"
I think Bill Sloman is the only one so far who knows what I'm asking. I
wonder which one of you guys it was that originally sent me off to study
the U113 app. note in the first place? I suspect it was Bill Sloman.
It seems that this is a complex subject. I may be insisting on my point
rather doggedly, but don't get me wrong. I know full well that I don't
know a great deal about this subject, so all of your comments are
carefully filed for later serious investigation. I hope that I can get
most of the maths and circuitry for the whole design process onto the
Actually, what might have led this thread astray is too much focus on
the 4046. Imagine that we are dealing with a 3-state detector. You
have designed a first order loop with it. It works. It runs with a
constant phase error as expected from a 1st order PLL. Now you want to
integrate the error to zero. You stick in an integrating term. Now
what do you do to compensate for the added negative slope of the |Kpd Kf
Kvco| open loop gain in order to maintain loop stability? Do you add a
*That* is the question.
Thanks for all the input. It's been interesting.
Christopher R. Carlen
Suse 8.1 Linux 2.4.19
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