From: Jim Thompson
Newsgroups: sci.electronics.design
Subject: Re: How to increase PLL order?
Message-ID:
References: <7c584d27.0212101440.54ba0336@posting.google.com>
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Date: Wed, 11 Dec 2002 15:43:14 GMT
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On Wed, 11 Dec 2002 04:39:05 GMT,
Chris Carlen ,
In Newsgroup: sci.electronics.design,
Article: ,
Entitled: "Re: How to increase PLL order?",
Wrote the following:
|Jim Thompson wrote:
|> |A 4046 type II (digital/charge pump) detector driving an R-C or R-C//C
|> |filter does give a type 2 closed loop: zero steady-state phase error.
|> |
|> |John
|>
|> Absolutely! Methinks Chris has some cockpit errors in his
|> experimental setup.
|>
|> ...Jim Thompson
|
|
|I never said I was driving an RC filter! Of course it will produce zero
|phase error with a RC filter, which integrates. But I am not driving an
|RC filter with it, but rather converting it into a strange sort of phase
|detector which produces a voltage proportional to the phase difference
|*without* integrating by pulling up on the z-state's output, then
|feeding to an RC with a pole at quite a high frequency, relative to the
|loop's unity gain frequency.
|
[snip]
I wonder if it is wise to be playing with "a strange sort of phase
detector" when you're new to PLL's?
Probably the most experienced comments have been posted by Roy
McCammon at....
Message-ID: <3DF74F69.94C06FF8@mmm.com.DELETETHIS>
Roy's approaches also have the nice feature of handling startup, where
all bets are usually off, and instabilities abound.
And, yes, you do need a zero ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
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