From: John Larkin
Subject: Re: microvia stackup questions
Date: Wed, 11 Dec 2002 08:35:45 -0800
Organization: Posted via Supernews, http://www.supernews.com
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On Wed, 11 Dec 2002 15:28:20 +0100, "Bernhard Mäder"
>We're doing a high speed design (133 MHz, no DDR, though) using micro via
>technology (top and bottom two layers). Now, the apparent stackup, aiming at
>an easy layout job, would be to chose the top three layers as follows:
>(followed by the core and sig, sig, gnd on the bottom side)
>Each (experienced...) engineer I ask in house here, told me to not do it
>this way, but to use a conventional (Signal, Ground, Signal) stackup in
>order to have a clean ground plane for the signal lines to reference to.
>My question is: what does one usually do and why? Isn't there an issue with
>the return current, since the top ground plane will be covered with holes
>and slittings (pads, short signal lines from the BGAs etc.)? And how about
>the impedance changes in the signal lines?
>Thanks for any suggestions
If you put a ground plane on the top, it will be all chopped up by
pads and vias, and you won't have very good grounds under chips; for
QFP-type packages, you won't have ground under the chips at all.
A good 6-layer stackup might be
1 sig, surfmount parts
3 power plane/islands, maybe a few sigs
6 sig, maybe bottom parts
Keep the 3-4 dielectric as thin as possible (5 mils or so); this forms
a better very-high-frequency bypass cap than any discrete capacitor
you can buy.
Try to route 1:2 and 5:6 traces at right angles for minimum crosstalk.
This also makes controlling impedances easier.
And remember, it's hard to kluge inner layers!