The Cyber-Spy.Com Usenet Archive Feeds Directly
From The Open And Publicly Available Newsgroup
This Group And Thousands Of Others Are Available
On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic,
Opinions Or Content Posted To This Or Any Other
Newsgroup. This Web Archive Of The Newsgroup And
Posts Are For Informational Purposes Only.
From: Keith Wootten
Subject: Re: One and only one pulse gate.
User-Agent: Turnpike/6.02-U (<7r9OMDU2ooRJCQmjnYJxyjtHfm>)
X-Inktomi-Trace: pc2-rdng1-6-cust50.winn.cable.ntl.com 1039630575 28227 18.104.22.168 (11 Dec 2002 18:16:15 GMT)
Date: Wed, 11 Dec 2002 18:15:55 +0000
NNTP-Posting-Date: Wed, 11 Dec 2002 18:16:16 GMT
Organization: ntl News Service
In message <firstname.lastname@example.org>, Tiger Phil
>I need to incorporate a gate in a TTL circuit that will only allow one
>and only one pulse in a pulse stream to go to the next stage. It must
>also be able to be reset manually(bounceless switch, etc.)
Assuming your pulse is lo-hi-lo, here's a simple way:
It's the hi-lo transition which needs to lock out subsequent pulses, so
start with your input signal connecting to the clock input of a negative
edge triggered D-type. Tie D Hi and connect Qbar to one input of an And
gate. Connect your input signal to the other And input and use the And
output as your one-shot signal.
Connect push button to Hi (with pull-down) to the active Hi clear input
of the D-type.
Push button, D-type is cleared taking Qbar Hi (and Q Lo) which allows
And to pass signal through. Negative edge on signal clocks D-type
setting Q Hi and Qbar Lo which locks out signal through And until reset
by push button.
As for actual chips, I dunno, see what's in the box. You may have an
active Lo clear on the D-type.
Go Back To The Cyber-Spy.Com
Usenet Web Archive Index Of
The sci.electronics.design Newsgroup