From: John Larkin
Subject: Re: How to increase PLL order?
Date: Wed, 11 Dec 2002 12:11:11 -0800
Organization: Posted via Supernews, http://www.supernews.com
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On Wed, 11 Dec 2002 04:09:20 -0000, firstname.lastname@example.org
(Bob Wilson) wrote:
>>A 4046 type II (digital/charge pump) detector driving an R-C or R-C//C
>>filter does give a type 2 closed loop: zero steady-state phase error.
>But it is sensitive to noise and will slip a cycle whenever it misses an
>edge. I presonally prefer using the exor (PD I), and stuffing lots of gain
>in the form of a simple integrator in the loop. The result is that phase
>shift across the lock range is now essentially zero (just like PD II), but
>it tolerates massive amounts of noise.
The disadvantage of an xor-type phase detector is its narrow seek
range. If the VCO frequency is far off the reference, the pd output
will be a high-frequency triangle that will be grossly attenuated by
the loop filter. In that case, the VCO will just wobble a little but
will not reliably walk toward lock. So there is a nasty, often
untenable tradeoff between phase noise and lock range. For crystal
oscillators, this is often not a problem, but with a wideband VCO this
can be lethal.
An AD9901 is the best of both worlds: it's 'digital' far from lock but
works in xor mode (no goofy deadbands like 4046 types) near lock. So
it always heads towards lock no matter how slow the loop filter.