The Cyber-Spy.Com Usenet Archive Feeds Directly
From The Open And Publicly Available Newsgroup
This Group And Thousands Of Others Are Available
On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic,
Opinions Or Content Posted To This Or Any Other
Newsgroup. This Web Archive Of The Newsgroup And
Posts Are For Informational Purposes Only.
From: email@example.com (Roy McCammon)
Subject: Re: mitigating charge injection in switched capacitor systems...
Date: Fri, 13 Dec 2002 11:12:00 -0600
X-Mailer: Mozilla 4.5 [en]C-CCK-MCD 3M/NCP 4.5 (WinNT; I)
Josh Model wrote:
> Hi all,
> I'm designing a correlated double sampler circuit for a pretty highly
> constrained system (space flight app). The rad tolerance spec pretty
> severely limits the choice of analog switches, and it would make my life
> much easier if I could find a clever way to reduce the "off" state charge
> injection (i.e. source leakage current) of my switch.
> From my understanding, at least one cause of charge injection is the
> source-gate capacitance of a FET switch, and a sort of fast switching time
> (10 to 100 ns range) creates a big dV/dt, resulting in a large leakage. One
> way to reduce the current leakage that leaps to mind (especially since I
> don't have to switch very fast -- 1 us range or maybe even a little slower)
> is to slow down my voltage change at the TTL control of the switch (i.e. the
> Anybody have any experience with this? Or any other design techniques to
> reduce leakage current?
Is it narrow band. Have you considered double heterodyne
Thank you for reading and or replying
If you are one in a million, there are 6000 people just like
Local optimization almost never yields global optimization.
Opinions expressed here are my own and may not represent those of my employer.
Go Back To The Cyber-Spy.Com
Usenet Web Archive Index Of
The sci.electronics.design Newsgroup