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Reply-To: "Kevin Aylward"
From: "Kevin Aylward"
Subject: Re: mitigating charge injection in switched capacitor systems...
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Date: Sat, 14 Dec 2002 08:28:36 -0000
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Ken Smith wrote:
> In article <_moK9.2019$X56.firstname.lastname@example.org>,
> Kevin Aylward wrote:
>> Ken Smith wrote:
>>> Yes. what happens is: a charge is capacitively coupled in from the
>>> gate to the source when the gate moves. The channel then becomes a
>>> very high resistance and traps this charge as the source of the FET.
>>> If you are making your own gate driver for the fet, you can control
>>> the shape of the switching wave form to reduce this effect quite a
>> Vary dubious if the load is also a capacitor. It wont matter what the
>> ramp time of the control voltage is. Its a capacitor divider.
Yes it is. Have you actually tried simulating this in Spice?
Hint: I have:-)
> until the FET turns off it is an RC circuit with the resistance
> being the channel resistance of the FET.
If you switch faster than the RC time constant, then the voltage accross
the resistor will peak at the switch voltage, so the resistor can not
> If the gate moves slowly,
> most of the charge goes to the driven electode and not onto the load
Ahmmm.... sort off, on *rare* occasions, depends on just how *slow* you
switch. Sure if you switch *very* *very* slow such that i=dv/dt * R
switch is small, then that can limit the feedthough voltage. However,
this effect is all but *useless* in sample and hold or switched
capacitor filter applications because you usually have to switch much
faster than any RC time constant.
Its actually a common misconception that you can slow down edges to
minimise feedthrough. It can only work when the system response required
is slow, e.g. an audio switch can be slowed to ms ramps.
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.
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