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From: Robert Baer
X-Mailer: Mozilla 4.75 [en] (Win98; U)
Subject: Re: mitigating charge injection in switched capacitor systems...
Date: Sat, 14 Dec 2002 09:29:27 GMT
NNTP-Posting-Date: Sat, 14 Dec 2002 01:29:27 PST
Organization: EarthLink Inc. -- http://www.EarthLink.net
Bill Sloman wrote:
> "Josh Model" wrote in message
> > Hi all,
> > I'm designing a correlated double sampler circuit for a pretty highly
> > constrained system (space flight app). The rad tolerance spec pretty
> > severely limits the choice of analog switches, and it would make my life
> > much easier if I could find a clever way to reduce the "off" state charge
> > injection (i.e. source leakage current) of my switch.
> > From my understanding, at least one cause of charge injection is the
> > source-gate capacitance of a FET switch, and a sort of fast switching time
> > (10 to 100 ns range) creates a big dV/dt, resulting in a large leakage.
> > way to reduce the current leakage that leaps to mind (especially since I
> > don't have to switch very fast -- 1 us range or maybe even a little
> > is to slow down my voltage change at the TTL control of the switch (i.e.
> > gate).
> > Anybody have any experience with this? Or any other design techniques to
> > reduce leakage current?
> > Thanks,
> > --Josh Model, a digital designer stumbling into the analog world
> > MIT Lincoln Laboratory
> > (change the at -> @ and the dot -> .)
> At that sort of switching speed, FET-based switches suffer severely from
> charge injection. Some FETs are better than others - the SD214 lateral
> DMOS-FET used to be very good.
> About the only switch that doesn't is the diode bridge, which has its own
> compensating unpleasantnesses, but you can use it to sample very quickly
> indeed, and Agilent certainly used to sell sets of four matched diodes for
> precisely this job.
> Bill Sloman, Nijmegen
That scheme was used in most of the sampling heads and probes made by
Tektronics (in the good old daze).
They got down to the 25pSec region if i remember correctly....
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