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From: "Christopher R. Carlen"
Subject: Re: 87% All that vector calculus paid off
Date: Mon, 23 Dec 2002 09:21:42 -0800
Organization: Sandia National Laboratories, Albuquerque, NM USA
References: <firstname.lastname@example.org> <email@example.com>
NNTP-Posting-Date: Mon, 23 Dec 2002 16:20:10 +0000 (UTC)
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Fritz Schlunder wrote:
> Err... Not really, reverse recovery time of a diode has pretty much nothing
> to do with its turn on/forward recovery characteristics. Reverse recovery
> time being the time it takes for the current to drop to some set level
> (usually 250mA in most test setups for testing reverse recovery time) when
> the diode goes from an intial state of forward conduction (usually 1A in
> most manufacturers' test setups) to reverse bias. As soon as the diode
> becomes reverse biased the current through the diode reverses direction and
> isn't significantly limited by the diode until the excess carriers get
> absorbed/get swept away after a finite amount of time. The reverse recovery
> time is a strong function of the forward current just prior to reverse bias
> (trr increases as the forward current increases). AFAIK forward recovery is
> the time it takes for the diode's forward voltage to drop to near (110%? for
> at least some manufacturers?) the steady state forward voltage after an
> initially reverse biased (and fully blocking, IE not in reverse recovery)
> diode becomes forward biased.
I see. Thanks for the explanation.
> These numbers (although still not very ideal) are allot more believable than
> the last ones. That extra 380V-325V = 55V of overshoot can probably mostly
> be attributed to the parasitic loop inductance going from one end of your
> inductor, through the diode, through the output capacitor, back around
> through your supply rails, through the input filter capacitor, and back to
> the other side of the boost inductor. On a breadboard if meticulous
> attention isn't paid to minimize this inductance it can become relatively
> substantial (but don't be discouraged breadboards can still be used quite
> effectively for testing out SMPS designs).
> It is a bit hard to calculate exactly what voltage overshoot impact this
> inductance will have since it involves allot of variables and time dependant
> functions (IE, turn off time of MOSFET, current in inductor, parasitic
> capacitances such as MOSFET drain-source capacitance). But for a quick and
> dirty analysis lets assume your diode current experiences a turn on di/dt of
> about 100A/us or 100,000,000 Amps/sec. Let us also assume that 5V of your
> 55V overshoot can be attributed to the diode forward recovery
> characteristic. Then using the formula:
> Where E is the electromotive force produced by inductor L with a given
> change in current versus time of (di/dt).
> 500nH or parasitic inductance is relatively large, but probably not too
> difficult to obtain on a breadboard. From the original layout from the
> pictures of your original circuit on your webpage, it doesn't look like
> layout is all that spectacular (all those probes and test leads hooked up,
> etc.), and 500nH might not be unrealistic.
Yes, the pictures show a previous experiment. The present experiment is
a little more carefully laid out, but still, I did not take great pains
to reduce parasitics. So this all makes sense. And indeed, for this
not-too-demanding SMPS circuit, the breadboard works perfectly well for
getting the basic ideas worked out.
Thanks for the input.
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
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