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From: "Harry Dellamano"
References: <email@example.com> <3E06A99F.776F9A81@ieee.org> <3E07486E.424879B1@ieee.org> <951O9.102279$4W1.firstname.lastname@example.org> <3E0A3631.4A5C4AC5@ieee.org> <email@example.com> <firstname.lastname@example.org>
Subject: Re: 87% ... Design requirements are here
X-Newsreader: Microsoft Outlook Express 6.00.2720.3000
Date: Sat, 28 Dec 2002 03:34:19 GMT
NNTP-Posting-Date: Fri, 27 Dec 2002 22:34:19 EST
"Chris Carlen" wrote in message
> Yeah, the problem with my FET is 1 ohm on resistance, which hasn't been
> too much of a problem, since I have been driving the gate hard and
> probably getting much lower than that. But when the system is running
> from an input voltage closer to the 11V that I am shooting for, it could
> lead to a substantial increase in losses.
> Also, you have brought up a very important factor, and that is the
> flyback time, which indeed must become much shorter in the plain boost
> You see I have not yet attempted to make 350V from the 11V input. I am
> currently working through my own design flows on how to reengineer the
> system to do the job from 11V input, and am leaning toward a cheap 100V
> FET with 0.2ohm on resistance IRFI520N, and using a 6.5:1 flyback
> transformer, which will limit the drain to <100V even in the presence of
> a 25% leakage spike above the reflected flyback voltage plus the maximum
> specified Vcc of 25V.
> I have calculated that the primary should be 8.4uH to run at 150kHz.
> Max on-time would be 3.34us to give a 10% dead-time even in the case of
> minimum input voltage (11V) and minimum output voltage (90V).
> Your design flow is very interesting, and I will save it for further
> study. I am adapting my own procedure from Pressman, but with my own
> ideas factored in. I hope to explain it all someday later.
> But what is interesting me now, is the idea of zero voltage switching,
> or constant off time switching (variable frequency with off time tuned
> to put the switch-on moment at the zero voltage point of the ring down
> period with inductor current flowing in the optimum direction). It
> seems that for a variable output voltage and variable load supply, that
> constant off time can't work, because the flyback time is uncertain.
> Thus it would seem necessary to implement a circuit that implements
> dynamic zero voltage switching, always turning the FET back on at the
> first zero voltage after the flyback.
> But then there is the question, which zero voltage point is the right
> one? I am currently trying to figure that out on paper. I can't do an
> experiment right now because I broke my TL3842 chip, and have to fix my
> circuit before I can do anything. Maybe I can try a few runs tomorrow.
> Do you see what I mean? Should you turn on when the drain hits zero
> after the flyback? At that point the inductor current is maximum in the
> negative direction. Or should you do it after the first 3/4 cycles of
> the ring, when the body diode has just turned off, the drain passes
> through zero again in the positive direction, and the inductor current
> is heading in the same direction that we want.
> It would seem that the first zero is the best point, since then you can
> capture all the left over energy stored after the flyback in the winding
> and drain capacitances, now stored in inductor current (the first
> quarter cycle of the ring down transfered it to the inductor), and
> simply add whatever new energy is needed to bring the inductor up to its
> intended level.
> Trouble is, the current in the inductor is flowing in the wrong
> direction, so it will have to pass through a current zero before we can
> add energy to it. That means it will dissipate power in the body diode
> anyway and transfer the rest of its energy to the drain and winding
> capacitances again.
> This phenomenon of the ring down with clamping action in a flyback is
> very intriguing and complicated. What really puzzles me is that since
> the voltage get's clamped at about -0.6V from the body diode, how can
> there be enough energy left after the first clamp for the ring to reach
> almost up to the output voltage on the second positive excursion, which
> indeed it does?
> It seems it can be partly explained by the highly non-linear capacitance
> of the drain, which is maximum when the drain voltage is low (is that
> right?). But what happens to the drain cap. at negative drain voltage?
> Is there charge storage in the body diode that accounts for some of it
> as well?
> I am eager to hear where you would choose to do the switch on, in a
> "zero voltage" switching scheme, and do you agree that this would be the
> best topology? Your circuit would be a "constant inductor energy"
> scheme, right? But what do you forsee of the following problem:
> You realize of course, that the motivation for the zero voltage
> switching scheme is to solve the problem of transfer function
> non-linearity that occurs when the flyback is simply allowed to ring, in
> a constant frequency topology. Then, the output power vs. duty cycle
> transfer function is a stair case instead of linear, due to the effect
> of turning the FET back on at different points in the ring down.
> This effect is extreme in the case of the boost. It seems to be
> mitigated somewhat if there is a flyback transformer, though I am not
> very sure why (probably due to lower impedances in the drain circuit?).
> I vaguely recall this to be true when I did the experiments on my web
> site. The effect was present, but not extreme. With my current setup,
> it is extreme. I mean, the output voltage barely changes at all with
> changing duty, then suddenly undergoes almost a step discontinuity, to
> another output voltage/power, then the process repeats as I turn the
> duty cycle pot.
> I will see what effect the 6.5:1 transformer has on this problem. It
> might smooth it out enough that a control loop could function, but it
> would probably have to operate with reduced bandwidth.
> Any light you can shed on this topic would be read with great interest.
> I hope "analog" and Harry can chime in a bit as well.
> It seems there are no off the shelf components to implement this sort of
> thing. One of them mentioned being able to do it with a quad comparator
> (and probably an op-amp too).
Chris, you're scary, how long have you thought of Zero Voltage Switching? I
stated that IMHO you were four levels behind Analog but you have jumped two
in the last few days. I have thought of ZVS for maybe 15 years but I am
You requirement of short circuit proof requires a secondary and drives the
circuit topology. Your simple Buck Converter will not meet this requirement.
You said a lot on ZVS and most is correct. When the voltage flies back and
turns on the FET's parasitic diode it is important to turn on the FET
channel ASAP for best efficiency. This must be done on the first crossing,
maybe within 400ns.
I really can't report on too much because I have your design to do and
Analog will probably kick my butt anyway. He has not said too much and I
want to see his design so I can learn something. Maybe he is not interested.
As far as "off the shelf components" it is really easy to do and you will
understand when you see it. The only reason you would not do it this way is
if the user states "fixed frequency" because certain harmonics may interfere
with other processing he may be doing. Also if you have multi channels that
have to current share equally.
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