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From: email@example.com (Hal Murray)
Subject: Re: + and - edge triggered latches?
Date: Sun, 05 Jan 2003 21:15:00 -0000
X-newsreader: xrn 9.02
Sender: murray@glypnod (Hal Murray)
>> | (xor
>> | gate) y-------- out
>> where the delay is an r-c or a few gates strung together.
>Wow, quite elegant solution. Thanks (to both)!!
One problem with the delay approach is making the delay long
enough to make sure that the clock pulse is long enough to
cleanly clock the FF. A spare gate or two may not be enough.
One approach if you have a spare FF, is to toggle the FF
on each clock edge and use the output of the FF as the
other input to the XOR gate. That makes the delay long
enough to make sure you have clocked the FF. It might
not work if you are using several different types of FF.
(The delay through the XOR gate is extra.)
That only works if the clock is slow relative to the
clock width that you need.
[This trick came from Peter Alfke of Xilinx.]
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