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From: "Jeff Verive"
Subject: Re: Help analysing a CMOS ring oscillator
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Tue, 7 Jan 2003 13:46:15 -0600
NNTP-Posting-Date: Tue, 07 Jan 2003 13:46:15 CST
Device capacitance is not constant, with Cgd being very complex during
switching intervals. Cgs and Cds are less troublesome in general, at least
until connected to the outside world. The best analysis is done by
accounting for charge (coulombs) around the ring. This requires knowledge
of charge distribution throughout the transistor structure, which can be
ascertained in SPICE by looking at switching currents vs. time. The current
waveform you see in Ig can be broken down into Igs and Ids, which can then
be converted to equivalent capacitor models by noting the different currents
for specific Vgs excursions. Be sure to include reasonable resistance in
the gate so the transient analysis shows the transitions cleanly. Too
little gate resistance can make the transitions too small to glean any
useful data from.
P.S. Never assume that kN and kP are necessarily well balanced. Ic
designers play lots of tricks to make the devices "act" this way, but the
real physics usually dictates that kP be larger (processing variations are
not as kind to designers of P-transistors, particularly in N wells on P
"Phil Aldis" wrote in message
> I'm trying to understand a standard CMOS ring oscillator but am having
> some difficulty analysing it quantitatively (roughly!).
> In one of the tests I measured the propogation time for two different
> types of CMOS. They are identical but case 2 has p-channels that are
> three times wider than case 1. The propogation time for case 2 is 75%
> of case 1.
> Now I know that roughly the propogation time of CMOS is...
> tProp = 0.5 * (tPropLowHigh + tPropHighLow) = (capacitanceLoad / 2 *
> Supply Voltage) * ( 1 / kP + 1 / kN)
> where kP and kN are the n and p device transconductance factor...
> these are given by k' * (W / L)
> so given that W is three times bigger in case 2, kP should be 3 times
> as big. If we assume that kP and kN were matched in case 1 then the
> case had a term 2/k, and case 2 has a term 4/3k, which is 66% smaller.
> Now my results were 0.75 * original, and I think that the difference
> might have something to do with the fact that the wider transistors
> might present a higher capacitance with a slower charge up time. Any
> change in resistance is already taken account of in the change in k,
> but capacitances have being lumped into the capacitanceLoad, so should
> we change this and by how much?? What change (roughly) in the lumped
> capacitance is yielded by this change in channel dimensions?
> I would massively appreciate some help on this...
> Phil Aldis
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