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Reply-To: "Kevin Aylward"
From: "Kevin Aylward"
References: <firstname.lastname@example.org> <email@example.com>
Subject: Re: Help analysing a CMOS ring oscillator
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Date: Wed, 8 Jan 2003 15:05:21 -0000
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Phil Aldis wrote:
> Thanks for your response - unfortunately I don't have time to simulate
> the circuit in SPICE. It's for a lab write-up and would be a bit
> beyond the scope.
> Is the difference in my experimental readings attributable to the
> lumped capicitance on average being bigger. I understand (now) that
> the device capicitance won't be constant but if represented the device
> change with a single 'average' change in C which resulted in the same
> change in gate delay - would this CLoad be an increase and so would
> the gate delay then increase slightly?
An issue here is that in an actual oscillator like this, the delay/phase
shift around the loop could be significantly different from that
calculated from a simple single stage analysis. The load of one stage
may be significant. I would say that the best way to analyse this in
practice, is to use spice, if you actually want to know how the whoule
oscillator is working.
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.
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