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From: "Jeff Verive"
References: <email@example.com> <firstname.lastname@example.org>
Subject: Re: Help analysing a CMOS ring oscillator
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Wed, 8 Jan 2003 13:18:08 -0600
NNTP-Posting-Date: Wed, 08 Jan 2003 13:18:08 CST
Indeed, the phase shift will depend on a number of factors, with polysilicon
resistance and complex gate capacitance hard to model. Nonetheless, it is
common to use a lumped capacitance for a first-order analysis of such
circuits. From the geometry, you should be able to calculate the gate poly
resistance. You can also use propagation delay to account for these items
To answer your question, CLoad is a sum of internal capacitance (including
capacitance due to the device package), external probe capacitance, and
external capacitance due to attached devices.
"Kevin Aylward" wrote in message
> Phil Aldis wrote:
> > Thanks for your response - unfortunately I don't have time to simulate
> > the circuit in SPICE. It's for a lab write-up and would be a bit
> > beyond the scope.
> > Is the difference in my experimental readings attributable to the
> > lumped capicitance on average being bigger. I understand (now) that
> > the device capicitance won't be constant but if represented the device
> > change with a single 'average' change in C which resulted in the same
> > change in gate delay - would this CLoad be an increase and so would
> > the gate delay then increase slightly?
> An issue here is that in an actual oscillator like this, the delay/phase
> shift around the loop could be significantly different from that
> calculated from a simple single stage analysis. The load of one stage
> may be significant. I would say that the best way to analyse this in
> practice, is to use spice, if you actually want to know how the whoule
> oscillator is working.
> Kevin Aylward
> SuperSpice, a very affordable Mixed-Mode
> Windows Simulator with Schematic Capture,
> Waveform Display, FFT's and Filter Design.
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