Reply-To: "Kevin Aylward"
From: "Kevin Aylward"
References: <firstname.lastname@example.org> <email@example.com>
Subject: Re: Help analysing a CMOS ring oscillator
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Thu, 9 Jan 2003 08:14:40 -0000
NNTP-Posting-Date: Thu, 09 Jan 2003 08:14:43 GMT
Jeff Verive wrote:
> "Kevin Aylward" wrote in message
>> Phil Aldis wrote:
>>> Thanks for your response - unfortunately I don't have time to
>>> simulate the circuit in SPICE. It's for a lab write-up and would be
>>> a bit beyond the scope.
>>> Is the difference in my experimental readings attributable to the
>>> lumped capicitance on average being bigger. I understand (now) that
>>> the device capicitance won't be constant but if represented the
>>> device change with a single 'average' change in C which resulted in
>>> the same change in gate delay - would this CLoad be an increase and
>>> so would the gate delay then increase slightly?
>> An issue here is that in an actual oscillator like this, the
>> delay/phase shift around the loop could be significantly different
>> from that calculated from a simple single stage analysis. The load
>> of one stage may be significant. I would say that the best way to
>> analyse this in practice, is to use spice, if you actually want to
>> know how the whoule oscillator is working.
> Indeed, the phase shift will depend on a number of factors, with
> polysilicon resistance and complex gate capacitance hard to model.
> Nonetheless, it is common to use a lumped capacitance for a
> first-order analysis of such circuits. From the geometry, you should
> be able to calculate the gate poly resistance. You can also use
> propagation delay to account for these items as well.
This is all true, but not the difficult bit.
> To answer your question, CLoad is a sum of internal capacitance
> (including capacitance due to the device package), external probe
> capacitance, and external capacitance due to attached devices.
This is not completely correct, it its a bit more complicated than this,
hence my post. CLoad is also due to the miller capacitance of the
following stage. However, the miller gain is itself a result of the load
capacitance on its output. This goes on all around the loop. There is
not an easy way to model this, imo.
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