From: "Jeff Verive"
References: <email@example.com> <firstname.lastname@example.org>
Subject: Re: Help analysing a CMOS ring oscillator
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Thu, 9 Jan 2003 09:14:51 -0600
NNTP-Posting-Date: Thu, 09 Jan 2003 09:14:52 CST
"Kevin Aylward" wrote in message
> Jeff Verive wrote:
> > To answer your question, CLoad is a sum of internal capacitance
> > (including capacitance due to the device package), external probe
> > capacitance, and external capacitance due to attached devices.
> This is not completely correct, it its a bit more complicated than this,
> hence my post. CLoad is also due to the miller capacitance of the
> following stage. However, the miller gain is itself a result of the load
> capacitance on its output. This goes on all around the loop. There is
> not an easy way to model this, imo.
Multiply the load capacitance by the gain for the given stage, if you want
to get a closer approximation. But remember that the use of inverting
feedback lowers overall gain and hence decreases Miller capacitance. Stable
ring oscillators often include gain limiting stages for this purpose (since
open loop gain is highly temperature and voltage dependent).
Anyway, you were looking for a simplified lumped Cload. Choose a reasonable
gain value, multiply by the physical load capacitance, and you should have a