Reply-To: "Kevin Aylward"
From: "Kevin Aylward"
References: <firstname.lastname@example.org> <email@example.com>
Subject: Re: Help analysing a CMOS ring oscillator
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Date: Sat, 11 Jan 2003 16:51:18 -0000
NNTP-Posting-Date: Sat, 11 Jan 2003 16:51:56 GMT
Jeff Verive wrote:
> "Kevin Aylward" wrote in message
>> Jeff Verive wrote:
>>> "Kevin Aylward" wrote in message
>>>> Jeff Verive wrote:
>>> Multiply the load capacitance by the gain for the given stage, if
>>> you want to get a closer approximation.
>> Ho hum.... That's the bloody point. You don't know the gain. The gain
>> depends on the load capacitance of the next stage (gm.Xload), the
>> capacitance of the next stage depends on the gain of the following
>> stage, the gain of that stage depends on the gain of the 1st stage,
>> hence you have to solve solve some simultaneous equations to get the
>> gain/phase of the loop.
> For a first-order approximation, you use DC gain.
Nope. DC gain is not relevant at all. The oscillator will oscillate when
the gain is around 1. This is way off from the DC gain. The HF gain is
gm.Xc, where Xc is the effective capacitance load.
> Then you look at
> the input impedance of the next stage, including Miller capacitances,
> and calculate AC gain and phase shift.
Ho hum *again*, and just why do you think that I am mentioning this? As
I explained, you can't calculate the miller capacitance because you
don't know the gain at high frequencies without *first* knowing the
>> But remember that the use of
>>> inverting feedback lowers overall gain and hence decreases Miller
>> This statement makes no sense.
> As someone in sales for a SPICE variant product, you really ought to
> do without the sarcasm.
It was not sarcasm. It was statement that what you wrote was not
meaningfull. Tyat is, it made no sense.
>This was intended to be a hint.
One, that on note of your following statement, is still meaningless.
> output drive perspective, Miller capacitance of the next stage can be
> reduced if stage gain is reduced.
This has nothing to do with the term "negative" feedback in general,
when you have not even explained to what negative feedback you are
referring to. How do you actually propose to reduce the miller gain with
negative feedback? Where are you applying this feedback?
I wanted to see if the poster
> would consider limiting gain to make his life easier (hence my
> suggestion in the paragraph which followed). However, I agree that
> my intent was unclear; I guess the hint was disguised too well.
It still is.
>>> Stable ring oscillators often include gain limiting
>>> stages for this purpose (since open loop gain is highly temperature
>>> and voltage dependent).
>> Open loop gain is not really important in itself. What matters is how
>> stable the phase is at temperature/volts. However, the effective
>> phase shift is supply voltage dependant, so you do want to stabilise
>>> Anyway, you were looking for a simplified lumped Cload.
>> I wasn't, the original poster was, and I was explaining that it is
>> not trivial to come up with the effective gain in a loop like this.
>> You cant easily calculate the miller capacitance, because you don't
>> know the gain, because it depends on knowing what the capacitance is
>> in the first place.
> Considering that the original poster had k, W, and L available, he
> could easily have calculated static capacitance.
No problem with that.
> The variation of
> Cgd in the switching interval makes calculation of a lumped parameter
> non-trivial. The capacitance variation can be calculated from the
> current waveform, or by looking at current distribution in the
> device; he knew W, L, and k, and presumably the gate oxide thickness,
> so the current distribution could be integrated over the switching
> interval to calculate Cgd(min) and Cgd(max). The latter method is
> more precise, but the former is easily done by simulation (and it
> would have been nice of you to offer to help this chap with the
> simulation. Good PR beats bad PR anyday, unless you can afford to
> piss off prospective customers with sarcasm). *********
You just don't get it do you. Worrying about the current distribution is
the least of your trouble. This bit is complete pointless until you can
calculate what the gain of the loop is with reasonable idolized values,
which is clear that you have have not got the slightest idea that this
needs to be done. This is not sarcasm, its pointing out that you have
missed the boat. At HF the things that matter are the capacitances and
the gm. They all interact with each other around the loop. Try actually
coming up with a formula for the gain around the loop and it will be
obvious what the problem is.
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