From: "Jeff Verive"
References: <email@example.com> <firstname.lastname@example.org>
Subject: Re: Help analysing a CMOS ring oscillator
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Mon, 13 Jan 2003 14:44:58 -0600
NNTP-Posting-Date: Mon, 13 Jan 2003 14:44:58 CST
"Kevin Aylward" wrote in message
> Nope. DC gain is not relevant at all. The oscillator will oscillate when
> the gain is around 1. This is way off from the DC gain. The HF gain is
> gm.Xc, where Xc is the effective capacitance load.
Gee, and where does that AC gain come from? Yes, you can oscillate with
unity gain, but the fact is that an inverter stage can be analyzed first as
a DC circuit (even Spice uses successive DC operating point interations to
determine AC gain). You seem to be losing sight of the poster's goal. The
equations he is using to calculate transistor gain (with k, W, and L) are DC
equations based on device geometries. How do you propose he calculate gm and
Xc, given k, W, L, and internode capacitances (and what assumptions do you
want him to make for substrate capacitances)?
> > Then you look at
> > the input impedance of the next stage, including Miller capacitances,
> > and calculate AC gain and phase shift.
> > *********
> Ho hum *again*, and just why do you think that I am mentioning this? As
> I explained, you can't calculate the miller capacitance because you
> don't know the gain at high frequencies without *first* knowing the
> millor gain.
Ho hum, and fiddle-dee-dee. You offer NOTHING of help, just some misguided
form of self-praise. Miller gain depends on the gain of the stage and the
physical capacitance. Look closely at the REAL (not idealized) equations
for gain/transconductance, and there you find Aol or Acl, which are DC
> >> But remember that the use of
> >>> inverting feedback lowers overall gain and hence decreases Miller
> >>> capacitance.
> >> This statement makes no sense.
> > ********
> > As someone in sales for a SPICE variant product, you really ought to
> > do without the sarcasm.
> It was not sarcasm. It was statement that what you wrote was not
> meaningfull. Tyat is, it made no sense.
> >This was intended to be a hint.
> One, that on note of your following statement, is still meaningless.
Nonesense - read on.
> >From the
> > output drive perspective, Miller capacitance of the next stage can be
> > reduced if stage gain is reduced.
> This has nothing to do with the term "negative" feedback in general,
> when you have not even explained to what negative feedback you are
> referring to. How do you actually propose to reduce the miller gain with
> negative feedback? Where are you applying this feedback?
If you don't know what negative (or inverting) feedback is, you have no
reason to be answering questions concerning device construction. Put in
some source impedance, and you get inverting feedback (increase in Id
increases Vs, which decreases Vgs - kid's stuff really). In addition, the
source impedance is reflected in the gate, which in series with the output
impedance of the previous stage forms a voltage divider. If you still
don't understand these concepts, read Horowitz and Hill.
> I wanted to see if the poster
> > would consider limiting gain to make his life easier (hence my
> > suggestion in the paragraph which followed). However, I agree that
> > my intent was unclear; I guess the hint was disguised too well.
> > ********
> It still is.
Obviously, you don' seem to be understanding much. Certainly not the best
face to put on for someone in sales.
> >>> Stable ring oscillators often include gain limiting
> >>> stages for this purpose (since open loop gain is highly temperature
> >>> and voltage dependent).
> >> Open loop gain is not really important in itself. What matters is how
> >> stable the phase is at temperature/volts. However, the effective
> >> phase shift is supply voltage dependant, so you do want to stabilise
> >> it.
> >>> Anyway, you were looking for a simplified lumped Cload.
> >> I wasn't, the original poster was, and I was explaining that it is
> >> not trivial to come up with the effective gain in a loop like this.
> >> You cant easily calculate the miller capacitance, because you don't
> >> know the gain, because it depends on knowing what the capacitance is
> >> in the first place.
> > *********
> > Considering that the original poster had k, W, and L available, he
> > could easily have calculated static capacitance.
> No problem with that.
> > The variation of
> > Cgd in the switching interval makes calculation of a lumped parameter
> > non-trivial. The capacitance variation can be calculated from the
> > current waveform, or by looking at current distribution in the
> > device; he knew W, L, and k, and presumably the gate oxide thickness,
> > so the current distribution could be integrated over the switching
> > interval to calculate Cgd(min) and Cgd(max). The latter method is
> > more precise, but the former is easily done by simulation (and it
> > would have been nice of you to offer to help this chap with the
> > simulation. Good PR beats bad PR anyday, unless you can afford to
> > piss off prospective customers with sarcasm). *********
> You just don't get it do you. Worrying about the current distribution is
> the least of your trouble. This bit is complete pointless until you can
> calculate what the gain of the loop is with reasonable idolized values,
> which is clear that you have have not got the slightest idea that this
> needs to be done. This is not sarcasm, its pointing out that you have
> missed the boat. At HF the things that matter are the capacitances and
> the gm. They all interact with each other around the loop. Try actually
> coming up with a formula for the gain around the loop and it will be
> obvious what the problem is.
I think the boat has missed you. The idealized values make you lose sight
of the actual contribution of DC gain to AC gain. The poster needs to
understand this in order to fully appreciate transistor design (and design
of transistor and IC circuits). At high frequencies, capacitive and
inductive reactances are certainly important, but the transconductance of
the transistor and the capacitance of the structures can be broken into
separate quantities, which is what the poster was trying to do. The
idealized loop gain equation does not hint at the underpinnings of the
problem, which can be found in the semiconductor device structural analysis.
This is not a "big picture" exercise, in which the smaller pieces can be
ignored. Since the poster was talking in terms of k, W, and L, he was
looking into device characteristics at the die level. If his instructor did
not give reasonable quantities for Cgd, it was pointless in trying to guess
at them, hence my suggestions to look at the movement of charges.
Bottom line - you CAN calculate Miller gain if you know open loop dc gain,
real capacitances and resistances (and inductances, for the really high
> Kevin Aylward
> SuperSpice, a very affordable Mixed-Mode
> Windows Simulator with Schematic Capture,
> Waveform Display, FFT's and Filter Design.