From: "Gary Richardson"
Subject: Re: PLL Questions
Date: Tue, 14 Jan 2003 15:02:12 -0800
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"John Larkin" wrote in
> On Tue, 14 Jan 2003 10:14:18 -0800, "Gary Richardson"
> >I'm trying to design a PLL circuit and have some questions. I read the
> >section in Chapter 9 of A of E on PLLs and think I've got the general
> >However, I'm not too clear on one point, how to pick the min and max
> >frequencies of the VCO. The frequency multiplier example (pages
> >647 - 650) generated an output signal of 61,440 Hz synchronized to 60 Hz
> >the limits on the VCO were 20 kHz to 200 kHz. Why such a wide range? Why
> >would the VCO tuning range not be centered on the target frequency, in
> >case 20 kHz to 100 kHz would seem to be more appropriate.
> >In my case I want to lock on to the 60 kHz WWVB signal.
> >What would be suitable min and max frequencies for that?
> Your VCO range only needs to be wide enough to guarantee lock, namely
> a bit more than the signal range plus possible tolerance+drift of the
> VCO itself. Since the WWVB signal is always exactly 60K, all the vco
> has to do is be able to be pulled to that frequency. If the VCO is a
> crystal oscillator, it would have a typical pull range of +-50 or
> maybe +-100 PPM, just enough to account for initial tolerance,
> temperature, and ageing.
> If the VCO has a pull range much wider than absolutely necessary, you
> pay the price of longer lock time, possible lock uncertainty, and
> excess phase noise.
As I indicated in my other post, I had planned to use the '4060 PLL chip,
primarily because that's the way A of E did it. However, using a crystal
oscillator as the VCO is very interesting and would probably work much
better. I think I'll give that a try. A of E shows how to do that on page
302. What a book!
Thanks for your reply.