From: "Jeff Verive"
References: <firstname.lastname@example.org> <_MgV9.email@example.com>
Subject: Re: Help analysing a CMOS ring oscillator
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Thu, 16 Jan 2003 12:01:11 -0600
NNTP-Posting-Date: Thu, 16 Jan 2003 12:01:11 CST
"Kevin Aylward" wrote in message
> Jeff Verive wrote:
> > Of course, I understand the relationship between gain-bandwidth
> > product and miller capacitance, which the original poster was having
> > a hard time modeling.
> Because it is a hard thing to model in a gm amplifier.
But not so hard when the next stage is a light load (like another inverter
> >No doubt infinite DC gain does little good if
> > unity gain is to be had at a crappy low frequency, but one can
> > estimate miller capacitance as an input capacitor nearly equal to
> > Cf(1-A), where A is the gain of the circuit with the feedback
> > reactive element Cf removed
> But this does not mean the gain without the *output load* effects of the
> feedback capacitor.
That's exactly what it means.
> >(i.e. the DC gain between gate and drain
> > when the feedback [miller] capacitance is removed, not the overall
> > amplifier gain).
> No you can't in a simple cmos inverter stage!!!!
Yes you can, the inverter has gain, which is a function of k, W, and L.
> You have missed a fundamental point of the millor theorem. It *only*
> works when the amplifier has a low output impedance such that the gain
> is not effected by any load. It *assumes* that A is independent of load,
> i.e. a voltage source. This is simply not true for a gm amplifier. It
> has a load of its own millor capacitor itelf, and the input impedance of
> the next stage. This changes the gain significantly.
You do it a stage at a time, if you are trying to analyze the ring.
> Go and do a small signal equivalent analysis before you keep putting
> your foot in it.
I've done the analysis, and the Cf mentioned above works well as long as you
take into account the non-linear Cgd.
> > BTW, the same approach is used in textbooks by Mauro, Schilling and
> > Belove, to name a few.
> But not with a *current* output amplifier.
> >The original poster could have modeled this
> > in many ways in SPICE to determine the effective miller capacitance,
> > but did not seem to be willing to do this, despite my urgings.
> There is no real point in modelling the miller capacitance. Just model
> the whole circuit all at once and be done with it. For starters, the
> miller capacitance isn't.
> Suppose I have an ideal gm source, with its output connected to its
> input, whats its input impedance.? How about 1/gm, irrespective of the
> feedback impedance?
> This shows how the input impedance of a gm stage depends crucially on
> its load. The problem in a feedback ring, is that it all goes in
> circles, making everything all interact with each other. You can't do a
> simple calculation.
You break the ring to analyze it, then reconnect it. Yes, it is not a
trivial example, but it can be done a stage at a time (which is what the OP
what looking for anyway).
> > Instead, he was looking for a lumped-parameter model that would be
> > useful as a first-order approximation. In the end, DC gain in a
> > simple inverter establishes an upper bound for AC gain (where Cgd is
> > the chief contributor to miller capacitance).
> But the DC gain, as I have explained many times is not relevant. You
> need to accept this fact. The miller gain is given by gm.Z. Where Z some
> effective load impedance due to its *own* millor capacitance and the raw
> gm of the following stage. It is *not* only due to ro of the mosfets.
A CMOS inverter stage cannot be modeled as a simple amplifier, but as two
switches driving small capacitances. The transistors are not biased into
their linear regions, where power consumption would be a huge problem. You
keep wanting to analyze this like a linear AC amplifier, and it is anything
but that. And even if it were an AC problem, Z is *not* dependent on gm of
the following stage.
> > If the source had some
> > bypass capacitance, or if bootstrapping, cascode connections, or
> > source follower stages are used, AC gain improvements and reductions
> > in miller capacitance are relatively easy to accomplish, but we have
> > to remember that the original poster was trying to analyze a simple
> > CMOS ring oscillator, in which none of these tricks are commonly
> > used.
> You keep using all these electronic terms to impress, yet you don't
> appear to actually know how to apply them.
I don't need to impress. I know how to use all the above terms in real world
examples (and have been doing so for over 25 years, succesfully). I
understand the OP's plight, and I also know how to get around it. The point
is that in CMOS inverters, the driving impedance is extremely low. with a
low source impedance, the miller theorem allows significant lattitude in
> > Kevin's not on the suds, though I'm sure he could have used some by
> > now (we all could). For some reason, after some dozens of replies,
> > the original poster's intent gets lost, and I try to keep the basic
> > problem in mind.
> The basic problem isn't. Its actually quite complicated. It took me
> several pages of calculations to come up with a correct formula for a
> simple 3 stage feedback ring where there was only a millor capacitor and
> a gm included in the model. I'll see if I have time to post the details
> on my site.
> Best Regards,
> Kevin Aylward
> SuperSpice, a very affordable Mixed-Mode
> Windows Simulator with Schematic Capture,
> Waveform Display, FFT's and Filter Design.