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From: firstname.lastname@example.org (James Osborne)
Subject: Re: PLL Questions
Date: 16 Jan 2003 16:33:11 -0800
NNTP-Posting-Date: 17 Jan 2003 00:33:11 GMT
I once designed a PLL for a precision oscillator and I used a CD4046.
I used a frequency divider and 60HZ precision oscillator IC. There are
a few different ways to obtain the error signal. The math is very
intense. If you do not have at least a BS in Math I'd say pass on
understanding all the details.
John Popelish wrote in message news:<3E261E29.email@example.com>...
> Gary Richardson wrote:
> > I'm trying to design a PLL circuit and have some questions. I read the
> > section in Chapter 9 of A of E on PLLs and think I've got the general idea.
> > However, I'm not too clear on one point, how to pick the min and max
> > frequencies of the VCO. The frequency multiplier example (pages
> > 647 - 650) generated an output signal of 61,440 Hz synchronized to 60 Hz and
> > the limits on the VCO were 20 kHz to 200 kHz. Why such a wide range? Why
> > would the VCO tuning range not be centered on the target frequency, in which
> > case 20 kHz to 100 kHz would seem to be more appropriate.
> > In my case I want to lock on to the 60 kHz WWVB signal.
> > What would be suitable min and max frequencies for that?
> If you are building one unit, and are willing to tweak the minimum and
> maximum, you can pull them in very close ot the expected operating
> frequency, and make lock in very much faster. But if you design for
> production, the range has to cover all tolerances that can affect
> frequency. A few percent for the chip, a couple percent for the
> resistors (if you use 1% resistors) and 5% for the capacitor, and you
> have something like +-10 % minimum, just to guarantee that a fixed
> frequency falls inside the operating range. Use cheaper parts, or
> plan on a wide temperature range, and +-20% is still pretty tight.
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