Reply-To: "Kevin Aylward"
From: "Kevin Aylward"
References: <email@example.com> <_MgV9.firstname.lastname@example.org>
Subject: Re: Help analysing a CMOS ring oscillator
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Fri, 17 Jan 2003 08:24:18 -0000
NNTP-Posting-Date: Fri, 17 Jan 2003 08:24:23 GMT
Jeff Verive wrote:
> "Kevin Aylward" wrote in message
>> Jeff Verive wrote:
>>> Of course, I understand the relationship between gain-bandwidth
>>> product and miller capacitance, which the original poster was having
>>> a hard time modeling.
>> Because it is a hard thing to model in a gm amplifier.
> But not so hard when the next stage is a light load (like another
> inverter stage).
But it isn't. Your assumption is false. The next sage is a gm stage with
A pure gm stage with miller feedback will have an input impedance of
1/gm, irrespective of what that miller feedback impedance is.
>>> No doubt infinite DC gain does little good if
>>> unity gain is to be had at a crappy low frequency, but one can
>>> estimate miller capacitance as an input capacitor nearly equal to
>>> Cf(1-A), where A is the gain of the circuit with the feedback
>>> reactive element Cf removed
>> But this does not mean the gain without the *output load* effects of
>> the feedback capacitor.
> That's exactly what it means.
You are wrong. Its that simple. This shows clearly that you have little
understanding of this issue.
The miller theorem say that if you *know* what the gain is, then you can
write zi=Zf/(1-A). Decent books will point out that if the gain is load
dependant than you don't know what A is.
Your confusion here is between breaking the loop to determine what the
gain is without feedback, and the separate concept that a load on an
amplifier will also effect its gain. This is a *standard* problem in
analysing feedback loops. Sure, you have to brake the loop, but you must
also include the load of that break on the output.
I suggest you do some more study on this.
>>> (i.e. the DC gain between gate and drain
>>> when the feedback [miller] capacitance is removed, not the overall
>>> amplifier gain).
>> No you can't in a simple cmos inverter stage!!!!
> Yes you can, the inverter has gain, which is a function of k, W, and
What is is gain at HF?
>> You have missed a fundamental point of the millor theorem. It *only*
>> works when the amplifier has a low output impedance such that the
>> gain is not effected by any load. It *assumes* that A is independent
>> of load, i.e. a voltage source. This is simply not true for a gm
>> amplifier. It has a load of its own millor capacitor itelf, and the
>> input impedance of the next stage. This changes the gain
> You do it a stage at a time, if you are trying to analyze the ring.
That's because you have to. As I keep pointing out, the load of one
stage effects the miller gain of the prior stage. You cannot separate
>> Go and do a small signal equivalent analysis before you keep putting
>> your foot in it.
> I've done the analysis, and the Cf mentioned above works well as long
You have made an error.
> as you take into account the non-linear Cgd.
>>> BTW, the same approach is used in textbooks by Mauro, Schilling and
>>> Belove, to name a few.
>> But not with a *current* output amplifier.
>>> The original poster could have modeled this
>>> in many ways in SPICE to determine the effective miller capacitance,
>>> but did not seem to be willing to do this, despite my urgings.
>> There is no real point in modelling the miller capacitance. Just
>> model the whole circuit all at once and be done with it. For
>> starters, the miller capacitance isn't.
>> Suppose I have an ideal gm source, with its output connected to its
>> input, whats its input impedance.? How about 1/gm, irrespective of
>> the feedback impedance?
>> This shows how the input impedance of a gm stage depends crucially on
>> its load. The problem in a feedback ring, is that it all goes in
>> circles, making everything all interact with each other. You can't
>> do a simple calculation.
> You break the ring to analyze it, then reconnect it.
What's the load on each stage? Post your formula. You still fail to
understand 101 feedback theory. You must include the load at the break
on the output of the amp.
I note that you simple fail to see the significance the input impedance
of a gm stage with feedback, as you ignored it above when claiming a
> Yes, it is not a
> trivial example, but it can be done a stage at a time (which is what
> the OP what looking for anyway).
No you can't. All parts of the circuit interact with each other. Post
>>> Instead, he was looking for a lumped-parameter model that would be
>>> useful as a first-order approximation. In the end, DC gain in a
>>> simple inverter establishes an upper bound for AC gain (where Cgd is
>>> the chief contributor to miller capacitance).
>> But the DC gain, as I have explained many times is not relevant. You
>> need to accept this fact. The miller gain is given by gm.Z. Where Z
>> some effective load impedance due to its *own* millor capacitance
>> and the raw gm of the following stage. It is *not* only due to ro of
>> the mosfets.
> A CMOS inverter stage cannot be modeled as a simple amplifier, but as
> two switches driving small capacitances.
As a first approximation, it is. especially, when running flat out.
> The transistors are not
> biased into their linear regions, where power consumption would be a
> huge problem.
There are when they are running full belt. Have you actually looked at a
cmos ring oscillator? It runs as a fair approximation to a sine wave.
This is because its running at the maxim frequency that the inverters
can run at.
Indeed, in a practicl cmos ring, the ouput might only swing a fraction
of the supply voltage.
>You keep wanting to analyze this like a linear AC
> amplifier, and it is anything but that.
It is for a first order analysis of the problem. I agree, that large
signals may well need further consideration.
> And even if it were an AC
> problem, Z is *not* dependent on gm of the following stage.
Course it is. I have explained many times why this is the case. Its
trivil amplifier theory. Have you never even looked at S parameters?
>>> If the source had some
>>> bypass capacitance, or if bootstrapping, cascode connections, or
>>> source follower stages are used, AC gain improvements and reductions
>>> in miller capacitance are relatively easy to accomplish, but we have
>>> to remember that the original poster was trying to analyze a simple
>>> CMOS ring oscillator, in which none of these tricks are commonly
>> You keep using all these electronic terms to impress, yet you don't
>> appear to actually know how to apply them.
> I don't need to impress. I know how to use all the above terms in
> real world examples (and have been doing so for over 25 years,
It looks more like 1 years of experience 25 times to me, as noted by
your complete lack of understanding of the details of miller theorem.
>I understand the OP's plight, and I also know how to
> get around it. The point is that in CMOS inverters, the driving
> impedance is extremely low. with a low source impedance, the miller
> theorem allows significant lattitude in gain assumptions.
Post you gain equations to prove this
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.