From: Winfield Hill
Subject: Re: frequency to voltage converter
Date: 17 Jan 2003 06:47:07 -0800
Organization: Rowland Institute
References: <firstname.lastname@example.org> <email@example.com>
X-Newsreader: Direct Read News 4.20
Winfield Hill wrote...
> Meindert Sprang wrote...
>> A different approach was published many years ago in Elektor.
>> They used a single CMOS flip-flop, triggered by the signal to
>> be measured. In series with the VSS pin and power ground was
>> a resistor and capacitor in parallel. They claimed that the
>> current draw of the FF was linear with the operating frequency,
>> thus creating a frequency dependent voltage over the resistor.
Oops, I missed Elektor's supply connection for sense resistor;
drawing and formula are corrected below.
. +5 Vdd ---------, Cute Frequency to Voltage Converter
. ,--|D Q|
. | | |
. f-in ---|--|> |
. | |___/Q|--,
. |____ | ____|
. | Vout = f R C (Vdd-Vout)/2
. R | Vout = f R C Vdd/2
. gnd--/\/\---' for very small Vout
> Cute. This is based on the classic formula i = C V f, where
> C is a logic circuit's switched capacitance. That's the amount
> of circuit capacitance that must be charged and discharged each
> cycle. Charge is taken from the supply, q = C V, and shunted
> to ground during discharge, completing the current path. The
> total current is I = q f, hence the formula above (the reader
> is invited to consider the 1/2 term in the output equation).
Wags will have realized that a flip-flop doesn't contribute to
the circuit, and can be replaced with a single logic inverter,
etc., removing the extra 2 from the equation. (See below.)
> With only an ordinary CMOS flip flip this current isn't very
> high at low frequencies, but one can add a capacitor to the
> output of the flip-flop, increasing the current as desired.
> Even with the added capacitor, the circuit is still simple and
> arguably is becoming even more cute, but sadly both versions
> have a serious flaw. In the i = C V f formula, V is the flip-
> flop's supply voltage. This means the frequency-measuring
> voltage dropped across the R-C in series with the logic supply
> reduces the V in our formula, destroying the circuit's linearity.
> The larger the output voltage of the cute f > V converter, the
> worse this effect. :>(
We can re-arrange the cute circuit's equation to highlight its
. Vout R C 1 R C
. ---- = f --- ( --------- ) ~= ( f - f^2 (RC)^2 ) ---
. Vdd 2 1 + fRC/2 2
. 2 Vout
. f = --- ---- ignoring the 2nd error term
. R C Vdd
Note the reduced effect of the 2nd term at low f and low Vout.
At 0.5V full-scale output Vout/Vdd = 0.1, so that f ~ 0.2/RC and
the effect of the second term is a sagging output-gain error of
about -10%, creating what, a 5% straight-line-fit error?
(But note, Vss = Vout must be kept under about 0.5V in the cute
f -> V circuits anyway, to avoid currents through the CMOS logic
IC input-protection diode when the logic input signal is low.)
Selecting R in the cute circuit for a maximum output of 50mV will
reduce the best-fit nonlinearity error to a possibly-acceptable
0.5% at full scale, but this also means the offset-voltage errors
of the required amplifier will produce a zero-frequency error,
limiting the frequency range of the circuit. E.g., a low 250uV
offset voltage would limit the 0 to FS operating range to only
200x, or 0.5% of full scale. So we're constrained with 0.5% low-
frequency zero error, plus 0.5% nonlinearity error at full scale
for an overall 1% error spec...
Replacing the flip flop with a logic-gate and adding an opamp,
here's our slighty-improved, cute, 1%-accurate F/V circuit.
It meets anotherbrick's spec for 5V out with a 1000 rpm motor
and attached 2500 pulse/rev encoder, +/-1% from 10 to 1000 rpm.
. Vr = +5V Cute Frequency to Voltage Converter
. |\| cmos gate Part values shown for
. "f" __| \__ 5.0V full scale at 41.7kHz
. from | / | C 1000pF ___________________________
. encoder |/| === 5% film | |
. | | __ LT1014C | Vout = 5V/1000 rpm, to 1% |
. ,---+--|----|+ \_______ |___________________________|
. + | | | ,-|-_/ |
. C2 === R | | 270k Vout == G f R C Vr (1 - f RC)
. 10uF | 200 | '--------+ C = 50uF/fmax for G = 100
. | | | trimpot 2.0k C2 =~ 1000 C, ripple filter
. gnd --+---+--+-- 500 ----' G_amp = 1 + R2/R1 = 120 here
A 10uF capacitor provides a 170Hz (f_FS/500) averaging filter
across the 20-ohm 50mV sense resistor. Because our 1.0nF
reference capacitor swamps the internal cmos capacitance, the
remaining gates in the IC can likely be used for other purposes
without affecting the circuit. :>)
> To solve this problem, one must create a supply voltage that
> doesn't change with load, and measure its current load, using
> a circuit something like this,
>. Linear Frequency to Voltage Converter
>. +12 etc. __
>. ---+---------------|+ \ A2
>. | | \___________ OUT
>. +----||----, | /
>. | R +----|-_/\ difference
>. '---/\/\---+ | amplifier,
>. | | INA105, etc.
>. __ | gnd
>. ,----|+ \ A1 D
>. | | >----G Q1 Vout = f R C Vcc/2
>. | ,-|-_/ S 2n7000
>. | | | Where C includes the
>. | '------------+--||-- gnd flip-flop's internal
>. | | low-Z FF capacitance.
>. | +5 Vcc | bypass
>. --+--------|>]----+ Trim R to calibrate.
>. __|__ C
>. ,--|D Q|--||-- gnd
>. | | |
>. f-in ---|--|> |
>. | |___/Q|--,
> In this circuit A1 serves to maintain the flip flop at the
> same voltage as the rest of the logic, and a Schottky diode
> prevents possible latchup at power turn-on. The flip flop's
> power pins are directly bypassed with a capacitor to supply
> the potentially-high switching currents during transitions.
> The current for the flip flop with its output-enhancing load
> capacitor is provided by MOSFET Q1, and is sensed by resistor
> R, which can be trimmed to calibrate for the imprecise value
> of C and the loading effect of the internal resistors in A2.
> Although my circuit should work well, and fixes the serious
> problem in Elektor's simple circuit, its complexity prevents
> it from being called cute.