From: shb*NO*SPAMfirstname.lastname@example.org (Si Ballenger)
Subject: Re: 74HC259 as a demultiplexer?
Date: Sat, 18 Jan 2003 06:11:24 GMT
Organization: maybe later...
NNTP-Posting-Date: Sat, 18 Jan 2003 06:11:29 +0000 (UTC)
X-Newsreader: Forte Free Agent 1.11/32.235
On Sat, 18 Jan 2003 04:30:26 GMT, "Ban"
>Si Ballenger wrote:
>> I'm trying to use a 74HC259 chip as a simple demultiplexer
>> connected to the parallel port data pins. What I wuld like to do
>> is use the 5v from one data pin to power the chip, and use three
>> other data pins as the 3 logic inputs (A0-A2). The chip can
>> perform several functions, but I just need the output lines
>> (Q0-Q7) on the chip to go to 5v depending on which of the 3 input
>> lines is at 5v. Looking at the function table in the below data
>> sheet, I would think to set the chip for this type of operation,
>> MR and LE lines would need to be connected to ground to keep them
>> low. Also, the D line would need to be connected to to Vcc to
>> keep it high. In this configuration I expected the output lines
>> to go high when combinations of the input lines are made high by
>> connecting them to Vcc. This doesn't seem to work (after
>> tinkering, I may need to use a "fresh" chip), so does anybody see
>> anything obvious in this setup that would not let this work?
>> Currently I'm just powering it with a couple of batterys to see
>> if it will work. Any info on this would be much appreciated!
>If you read the datasheet right, you should have understood that the
>latch_enable line has to be toggled before the data can reach the output.
>Study a bit about logic functions and then figure out the diagramm on page5.
>The truth table clearly states that this decoder is not transparent.
>What you want is probably a 74HC138, but there the outputs are inverted
>(useful to drive FET switches).
Thanks for the info. looking more at the diagram, looks like the
LE performs a reset of the logic. The question now would be what
is the proper logic to follow. I would assume that the input
lines could be set as desired, the LE set high to reset the chip
logic, then set LE low to allow output to the desired output.
Looking at the delay diagrams, it appears that the LE is set high
first, then the input lines are set high, then LE is set low.
Does setting the inputs high first or LE high first matter? If
the input lines and LE could be set high at the same time, then
LE set low, this might save a gyration on the parallel port. I
could order some 74HC238 chips from Mouser to do the job, but for
this project I'm trying to stay with parts that are still
available at Radio Shack (which are very few now).