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From: "Anthony Q. Bachler"
Subject: Re: 65816 CPU @ 20MHz and 70ns EEPROM?
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Mon, 20 Jan 2003 16:23:06 -0600
NNTP-Posting-Date: Mon, 20 Jan 2003 17:23:52 EST
There are 2 solutions that I can see, depending on how much of an issue
price is, I'm assuming it is an issue since you don't want to just buy the
faster EPROM's but Ill include the other solution just for arguments sake.
1. Cheap solution - reduce the clock speed of the processor to 14 MHz or
pray that the EPROM is under-rated.
2. Fancy solution - Implement an external L1 cache so that the cache can
fetch two sequential bytes simultaneously (use a 27C64 for example with a 16
bit data bus). If a requested byte is not in the cache, drive RWB low until
the cache has time to fetch the proper address.
If this were a production requirement, I would go with springing for the
higher speed memory. If its a school assignment I would definitely go with
the cache design for an almost guaranteed A+++. There are also a few tricks
you can use to increase cache efficiency once you have it implemented, like
pre-decoding branch instructions and preemptively fetching the first 2 bytes
at the target location.
"If a million people say a foolish thing, it is still a foolish thing."
Anatole France [Jacques Anatole Thibault] (1844-1924)
"Krystian Sergiejew" wrote in message
> I am designing a single board computer that will use 65816 (W65C816S) at
> 20MHz. From my calculations it seems that 20MHz clock has a cycle of 50ns.
> How can I use a 70ns (or 120ns) EEPROM and still be able to read its
> contents? Do I have to implement wait states? How would one go about doing
> that with 65816?
> Any input will be highly appreciated.
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