From: "Anthony Q. Bachler"
Subject: Re: 65816 CPU @ 20MHz and 70ns EEPROM?
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Date: Tue, 21 Jan 2003 04:52:50 -0600
NNTP-Posting-Date: Tue, 21 Jan 2003 05:53:33 EST
CE is chip enable, used in memory bank arrays, think of it as an extra
address input but its only valid in one state, in the other state the data
outputs are generally in Hi-Z mode.
OE is Output enable, similar to CE except that when CE is false the chip
itself does not drive its internal data lines, where with OE it does, but
latches the output buffers to Hi-Z unless OE is true.
OE to Output Delay is the maximum time in nS from the true going edge of the
OE signal until the data at the data outputs is valid, basically the time it
takes the output buffers to go from the Hi-Z state to driving the data
OE to Output float is just the opposite, the maximum time from the false
going edge of OE until the data outputs are guaranteed to be in Hi-Z.
Output hold allows you to temporarily latch the output of the data lines so
that you can change the address lines without the data lines updating.
"If a million people say a foolish thing, it is still a foolish thing."
Anatole France [Jacques Anatole Thibault] (1844-1924)
"Krystian Sergiejew" wrote in message
> > I would read EPROM datashee. I am sure there are all the timings.
> Here is the EEPROM datasheet:
> However, I am just an amateur trying to learn electronics and computer
> architecture, and timings the way they are described in the data sheets
> simply not readable to me. Can anyone explain in plain English what the
> following means with the reference to the data sheet?
> Address to Output Delay
> CE to Output Delay
> OE to Output Delay
> OE to Output Float
> Output Hold
> I understand what CE and OE are, I am just not sure what is meant by these
> output delays.