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From: David Harmon
Subject: Re: 65816 CPU @ 20MHz and 70ns EEPROM?
Reply-To: David Harmon
X-Newsreader: Forte Agent 1.91/32.564
Date: Tue, 21 Jan 2003 23:06:01 GMT
NNTP-Posting-Date: Tue, 21 Jan 2003 15:06:01 PST
On Tue, 21 Jan 2003 08:51:45 GMT in sci.electronics.design,
"Krystian Sergiejew" wrote:
>Can anyone explain in plain English what the
>following means with the reference to the data sheet?
These are really best explained by the timing diagrams that accompany the
spec tables. The various time parameters are marked with reference to
some change of state of some signal; that means they are constraints on
the allowed timing of those changes of those particular signals. Also,
pay attention to whether each time is specified as a minimum, maximum, or
>Address to Output Delay
You must wait at least this long, after the address lines are stable,
before you can safely expect the outputs to be valid.
>CE to Output Delay
You must wait at least this long after Chip Enable is asserted before you
can expect the outputs to be valid.
>OE to Output Delay
Likewise, after Output Enable.
>OE to Output Float
You must wait at least this long, after Output Enable is De-asserted,
before you can depend on the outputs being floated so that you can safely
enable something else to drive the buss.
tOH is specified as min 0. That means after the address lines are no
longer stable, you cannot assume the outputs will remain stable for any
time at all.