From: John Larkin
Subject: Re: ground loops, optoisolators, and ADC noise, oh my!
Date: Tue, 21 Jan 2003 16:33:36 -0800
Organization: Posted via Supernews, http://www.supernews.com
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On 21 Jan 2003 10:15:12 -0800, email@example.com (Steve T
> I've been working on my first mixed-signal board for about 9 months
>now, and just when I was really excited that things were going to work
>(the amplifier section exceeds design specs!) I soldered on the first
>of my ADCs and found... that the conversion process generates
>fantastic noise. The ADC's input, when running, shows literlly 10-20
>mV of noise on each conversion cycle. This is with a scope probe --
>the digital output shows the same noise, of course. Now, this board
>has multiple simultaneously-sampling ADCs, so I run the /CONVST line
>to all of them from the output of an FPGA (Sampling below 300 khz). My
>fear is that the large area of current return is causing the problem
>-- CONVST must go from the FPGA, to the adc, out an adc ground and the
>flow along the analog plane back to the junction between analog and
>digital planes. What I would really like is some sort of galvanic
>isolation for this CONVST signal...
>I've been looking at optoisolators but they're expensive and slow.
>Plus, they all show propagation times that don't seem that suitable --
>they vary markedly with temperature and input current, all of which
>would contribute (50-100 nS in some cases) of jitter to the CONVST. In
>one of the analog devices app notes it is mentioned that people have
>used differential signalling (Such as ECL) for transmitting this sort
>of pulse... I'm curious as to how differential signalling gets around
>the problem of current return, and if anyone has used this or any
>other technique in the past to provide sample clock isolation...
Using separate analog and digital ground planes guarantees a potential
difference between the analog and digital ground planes. Some people
like that idea, but in a large system it can be hard to live with.